aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* anv: Allocate surface states per-subpassJason Ekstrand2020-04-282-119/+138
| | | | | | | | | | Instead of allocating surface states for attachments in BeginRenderPass, we now allocate them in begin_subpass. Also, since we're zeroing things, we can be a bit cleaner about or implementation and just fill out all those passes for which we have allocated surface states. Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Split command buffer attachment setup in threeJason Ekstrand2020-04-281-101/+144
| | | | | | | | | | | | | | | This commit splits genX(cmd_buffer_setup_attachments)() into three functions: one which sets up cmd_buffer->state.attachments, one which allocates surface states, and one which fills out the surface states. While we're here, we make both functions take the framebuffer (if any) as an argument instead of pulling it from the command buffer so it's more clear what things are inputs to the functions. We also make the render pass and framebuffer parameters const as those are immutable objects. The only functional change here should be that we now vk_zalloc the attachments which should be a bit safer. Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Mark images written in end_subpassJason Ekstrand2020-04-281-43/+53
| | | | | | | | | This makes a lot more sense than marking them written in begin_subpass since, at that point, we haven't written them yet. This should reduce the chances of accidental extra resolves. Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Use ANV_FROM_HANDLE for pInheritanceInfo fieldsJason Ekstrand2020-04-281-6/+10
| | | | | Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Assert surface states are validJason Ekstrand2020-04-281-0/+5
| | | | | Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Stop filling out the clear color in compute_aux_usageJason Ekstrand2020-04-281-7/+6
| | | | | | | | It's a pointless micro-optimization that just makes compute_aux_usage unnecessarily entangled with setting up surface states. Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Add TRANSFER_SRC to pass usage not subpass usageJason Ekstrand2020-04-282-3/+16
| | | | | | | | | | | The subpass usage flags are supposed to always be one bit and never multiple bits. However, when adding in TRANSFER_SRC usage for resolve attachments we were adding it to the subpass bits and not the render pass bits. This potentially is causing issues where images aren't getting marked written properly. Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* anv: Return an error if allocating attachment memory failsJason Ekstrand2020-04-281-0/+4
| | | | | Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
* radv: advertise VK_AMD_memory_overallocation_behaviorSamuel Pitoiset2020-04-283-0/+8
| | | | | | | | | | Doom Eternal explicitly allows overallocation via this extension but that shouldn't change anything because it's the default RADV behavior. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
* radv: track memory heaps usage if overallocation is explicitly disallowedSamuel Pitoiset2020-04-282-0/+48
| | | | | | | | | | | | | By default, RADV supports overallocation by the sense that it doesn't reject an allocation if the target heap is full. With VK_AMD_overallocation_behaviour, apps can disable overallocation and the driver should account for all allocations explicitly made by the application, and reject if the heap is full. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
* radv: remove unused radv_device_memory::map_size fieldSamuel Pitoiset2020-04-281-1/+0
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4785>
* nir/algebraic: Require operands to iand be 32-bitIan Romanick2020-04-281-4/+4
| | | | | | | | | | | | | | | | With the mask value 0x80000000, the other operand must be 32-bit. This fixes failures in dEQP-VK.subgroups.ballot_mask.ext_shader_subgroup_ballot.*.gl_subgroupgemaskarb_* tests from Vulkan 1.2.2 CTS. Checking one of the tests, it appears that the tests are doing 64-bit iand with 0x0000000080000000, then comparing the result with zero. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2834 Fixes: 88eb8f190bd ("nir/algebraic: Simplify logic to detect sign of an integer") Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4770>
* freedreno/ir3/ra: only assign array base in first passRob Clark2020-04-281-1/+2
| | | | | | | | | | In particular, we specifically don't want to let the base change between passes, as it could end up conflicting with registers assigned in the first pass. Mostly-closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2838 Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
* freedreno/ir3/ra: split out helper for array assignmentRob Clark2020-04-281-48/+58
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
* freedreno/ir3/ra: use ir3_debug_print helperRob Clark2020-04-281-8/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
* freedreno/ir3/ra: remove unused variableRob Clark2020-04-281-2/+0
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
* freedreno/computer: add script to test widening/narrowingRob Clark2020-04-281-0/+297
| | | | | | | | Just something I hacked together to help figure out which instructions can fold in a wideing/narrowing conversion. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4780>
* pan/bi: Add initial fcmp testAlyssa Rosenzweig2020-04-281-0/+44
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bit: Interpret CMPAlyssa Rosenzweig2020-04-281-1/+41
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bit: Prepare condition evaluation for vectorsAlyssa Rosenzweig2020-04-281-9/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Relax double-abs conditionAlyssa Rosenzweig2020-04-281-1/+1
| | | | | | | Only if both ports (<==> registers) same. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Pack fma.fcmp16Alyssa Rosenzweig2020-04-282-0/+23
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Factor out fp16 abs logicAlyssa Rosenzweig2020-04-281-17/+25
| | | | | | | Also used for fcmp16 Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Pack FMA 32 FCMPAlyssa Rosenzweig2020-04-282-0/+85
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Fix source mod testing for CMPAlyssa Rosenzweig2020-04-281-4/+5
| | | | | | | Outputs u32. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify ADD ICMP 32Alyssa Rosenzweig2020-04-281-0/+10
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify FMA ICMP 16Alyssa Rosenzweig2020-04-281-0/+8
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify FMA ICMP 32Alyssa Rosenzweig2020-04-281-0/+17
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify ADD FCMP16Alyssa Rosenzweig2020-04-281-0/+14
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify FMA FCMP16Alyssa Rosenzweig2020-04-281-0/+15
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi Strucitfy ADD FCMP 32Alyssa Rosenzweig2020-04-281-0/+11
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Structify FMA FCMPAlyssa Rosenzweig2020-04-281-0/+21
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Remove bi_round_opAlyssa Rosenzweig2020-04-283-12/+0
| | | | | | | No purpose. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Deduplicate csel/cmp condAlyssa Rosenzweig2020-04-286-12/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi(t): Fix SELECT testsAlyssa Rosenzweig2020-04-283-4/+4
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add CSEL.8 opcodeAlyssa Rosenzweig2020-04-281-0/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add FCMP.GL.v2f16 on ADD opcodeAlyssa Rosenzweig2020-04-281-0/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add 64-bit int comparesAlyssa Rosenzweig2020-04-281-0/+7
| | | | | | | Likewise. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add some 8-bit comparesAlyssa Rosenzweig2020-04-281-0/+3
| | | | | | | Not all but enough to see the pattern. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add CSEL.64 opcodeAlyssa Rosenzweig2020-04-281-0/+1
| | | | | | | Chain twice for full 64-bit CSEL. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* pan/bi: Add bool->float opcodesAlyssa Rosenzweig2020-04-281-0/+2
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4789>
* radv: enable FMASK for color attachments onlySamuel Pitoiset2020-04-281-1/+2
| | | | | | | | | | | | | | | The reason behind this is that FMASK requires CMASK and also that FMASK for non color attachments looks unnecessary. It's currently much easier to add this simple check because the driver tries to always enable DCC first and if we enable FMASK only if CMASK, we might loose some FMASK compressions. This helps fixing some new robustness2 tests which fails because only FMASK is enabled. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4783>
* anv: Expose CS workgroup sizes based on a maximum of 64 threadsJason Ekstrand2020-04-281-1/+2
| | | | | | | | | Otherwise, we'll hit asserts in brw_compile_cs. Fixes: cf12faef614ab "intel/compiler: Restrict cs_threads to 64" Closes: #2835 Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4746>
* intel/devinfo: Compute the correct L3$ size for Gen12Jason Ekstrand2020-04-281-0/+11
| | | | | | | Fixes: 8125d7960b6 "intel/dev: Add preliminary device info for Tigerlake" Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Clayton Craft <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4782>
* radv: Determine memory type for import based on fd.Bas Nieuwenhuizen2020-04-281-17/+63
| | | | | | | | | | This would be necessary for an application to figure out if the memory was allocated using a memory type with VK_MEMORY_PROPERTY_PROTECTED_BIT. It also allows one to determine VRAM vs. GTT etc. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
* radv/winsys: Add function to get domains/flags from fd.Bas Nieuwenhuizen2020-04-282-0/+51
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
* radv: Stop using memory type indices.Bas Nieuwenhuizen2020-04-282-108/+23
| | | | | | | | | | Lots of extra coding was involved in managing them. And for protected memory I was thinking of making a function that goes from domain+flags to memory types, which can reuse this array. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
* radv: Use actual memory type count for setting app-visible bitset.Bas Nieuwenhuizen2020-04-281-1/+1
| | | | | | | | Otherwise we might make a bitset that is too large. Cc: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4751>
* radeonsi: Count planes for imported textures.Bas Nieuwenhuizen2020-04-281-0/+9
| | | | | | | | | | | | | | | | For the DRI2 lowered YUV import separate pipe_resources get created but in the end the first resource just gets asked for NPLANES. Since 1) (Almost) everything uses the first resource + a plane index in the Gallium interface. 2) This mirrors non-imported textures. lets fix this in the driver. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4779>
* r600: Enable tesselation for NIRGert Wollny2020-04-281-3/+2
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4714>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 19:54:51 +0000