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* intel/perf: constify accumlator parameterLionel Landwerlin2019-04-172-3/+3
* intel/perf: drop counter size fieldLionel Landwerlin2019-04-174-9/+26
* i965: perf: add mdapi pipeline statistics queries on gen10/11Lionel Landwerlin2019-04-172-1/+10
* intel/perf: stub gen10/11 missing definitionsLionel Landwerlin2019-04-171-0/+4
* i965: move mdapi guid into intel/perfLionel Landwerlin2019-04-172-2/+4
* i965: move mdapi result data format to intel/perfLionel Landwerlin2019-04-177-98/+138
* i965: move brw_timebase_scale to device infoLionel Landwerlin2019-04-176-19/+22
* i965: move OA accumulation code to intel/perfLionel Landwerlin2019-04-175-199/+229
* i965: move mdapi data structure to intel/perfLionel Landwerlin2019-04-173-97/+128
* i965: extract performance query metricsLionel Landwerlin2019-04-1731-866/+1098
* i965: store device revision in gen_device_infoLionel Landwerlin2019-04-174-6/+5
* intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27Topi Pohjolainen2019-04-171-7/+17
* virgl: document potentially failing blitErik Faye-Lund2019-04-171-0/+6
* virgl: do color-conversion during when mapping transferErik Faye-Lund2019-04-171-10/+70
* virgl: only blit if resource is readErik Faye-Lund2019-04-171-2/+5
* virgl: get readback-formats from hostErik Faye-Lund2019-04-173-0/+44
* gallium/util: support translating between uint and sint formatsErik Faye-Lund2019-04-171-0/+62
* virgl: make sure bind is set for non-buffersErik Faye-Lund2019-04-171-0/+3
* virgl: support write-back with staged transfersErik Faye-Lund2019-04-172-22/+49
* virgl: use pipe_box for blit dst-rectErik Faye-Lund2019-04-171-5/+12
* virgl: rewrite core of virgl_texture_transfer_mapErik Faye-Lund2019-04-171-36/+58
* virgl: return error if allocating resolve_tmp failsErik Faye-Lund2019-04-171-0/+4
* virgl: wait for the right resourceErik Faye-Lund2019-04-171-1/+1
* virgl: check for readback on correct resourceErik Faye-Lund2019-04-171-1/+1
* virgl: make unmap queuing a bit more straight-forwardErik Faye-Lund2019-04-171-5/+7
* virgl: simplify virgl_texture_transfer_unmap logicErik Faye-Lund2019-04-171-13/+9
* virgl: track full virgl_resource instead of just virgl_hw_resErik Faye-Lund2019-04-171-5/+5
* virgl: tmp_resource -> templErik Faye-Lund2019-04-171-4/+3
* virgl: remove pointless transfer-counterErik Faye-Lund2019-04-174-4/+2
* radeonsi/nir: fix scanning of bindless imagesTimothy Arceri2019-04-171-38/+37
* iris: Add texture cache flushing hacks for blit and resource_copy_regionKenneth Graunke2019-04-161-0/+36
* v3d: Always set up the qregs for CSD payload.Eric Anholt2019-04-161-10/+2
* v3d: Only look up the 3rd texture gather offset for non-arrays.Eric Anholt2019-04-161-1/+1
* spirv: Tell which opcode or value is unhandled when failingCaio Marcelo de Oliveira Filho2019-04-164-42/+61
* spirv: Add more to_string helpersCaio Marcelo de Oliveira Filho2019-04-162-3/+15
* intel/mi_builder: Disable mem_mem tests on IVBJason Ekstrand2019-04-161-0/+3
* iris: Change vendor and renderer stringsKenneth Graunke2019-04-161-1/+4
* intel/mi_builder: Re-order an initializerJason Ekstrand2019-04-161-2/+2
* nir/algebraic: Use a cache to avoid re-emitting structsJason Ekstrand2019-04-161-17/+36
* nir/algebraic: Move the template closer to the render functionJason Ekstrand2019-04-161-19/+19
* iris: Move iris_debug_recompile calls before uploading.Kenneth Graunke2019-04-161-33/+33
* iris: Print the reason for shader recompiles.Kenneth Graunke2019-04-161-6/+30
* i965: Move program key debugging to the compiler.Kenneth Graunke2019-04-1613-283/+275
* winsys/amdgpu: don't set GTT with GDS & OA placements on APUsMarek Olšák2019-04-161-9/+11
* nir: optimize gl_SampleMaskIn to gl_HelperInvocation for radeonsi when possibleMarek Olšák2019-04-164-2/+48
* st/va/enc: Add support for frame_cropping_flag of VAEncSequenceParameterBuffe...suresh guttula2019-04-161-0/+8
* radeon/vce:Add support for frame_cropping_flag of VAEncSequenceParameterBuffe...suresh guttula2019-04-161-2/+9
* vl: Add cropping flags for H264suresh guttula2019-04-161-0/+5
* compiler/glsl: handle case where we have multiple users for typesTapani Pälli2019-04-168-11/+66
* intel/compiler: Do not reswizzle dst if instruction writes to flag registerDanylo Piliaiev2019-04-161-0/+6