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* mesa: fix mismatch when returning 64-bit bindless uniform handlesSamuel Pitoiset2017-07-281-1/+2
| | | | | | | | | | | | | The slower convert-and-copy process performs a bad conversion because it converts the value to signed 64-bit integer, but bindless uniform handles are considered unsigned 64-bit. This fixes "Check glUniform*() with mixed texture units/handles" from arb_bindless_texture-uniform piglit. Signed-off-by: Samuel Pitoiset <[email protected]> Cc: "17.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove gl_sync_object::Type fieldSamuel Pitoiset2017-07-282-5/+1
| | | | | | | This is useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: drop fence type parameter from NewSyncObject()Samuel Pitoiset2017-07-285-15/+9
| | | | | | | This is useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registersMarek Olšák2017-07-283-2/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rely on CLEAR_STATE for resetting the framebuffer and sample maskMarek Olšák2017-07-281-3/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use CLEAR_STATE to initialize some registersMarek Olšák2017-07-281-54/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: release sampler views when redefining a texture in st_context_teximageMarek Olšák2017-07-281-0/+2
| | | | | | | Noticed randomly. Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: for stencil only set Z tile mode index to same valueDave Airlie2017-07-281-0/+2
| | | | | | | | | | | | On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: drop precise modifier.Dave Airlie2017-07-281-0/+10
| | | | | | | | | The host doesn't understand this yet, so drop it for now. Fixes: virgl regressions. Fixes: af22adee4f (tgsi: add precise flag to tgsi_instruction) Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: always unconditionally revalidate main framebuffer after SwapBuffersMarek Olšák2017-07-281-0/+10
| | | | | | | | | This fixes the black Feral launcher window. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867 Cc: 17.2 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* radeonsi: bail out instead of crashing if the main shader part failed to compileNicolai Hähnle2017-07-271-0/+3
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi: update a comment for merged shadersNicolai Hähnle2017-07-271-1/+5
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi/gfx9: dump previous stage LLVM IR for merged shadersNicolai Hähnle2017-07-271-0/+7
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi: make sure TCS main output VGPRs don't alias inputsNicolai Hähnle2017-07-271-5/+13
| | | | | | | Avoids an unnecessary move introduce by "radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)" Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)Nicolai Hähnle2017-07-272-33/+79
| | | | | | | | | | | | | | | | | | With merged ESGS shaders, the GS part of a wave may be empty, and the hardware gets confused if any GS messages are sent from that wave. Since S_SENDMSG is executed even when EXEC = 0, we have to wrap even non-monolithic GS shaders in an if-block, so that the entire shader and hence the S_SENDMSG instructions are skipped in empty waves. This change is not required for TCS/HS, but applying it there as well simplifies the logic a bit. Fixes GL45-CTS.geometry_shader.rendering.rendering.* v2: ensure that the TCS epilog doesn't run for non-existing patches Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: fix vertex idx in ES with multiple waves per threadgroupNicolai Hähnle2017-07-271-1/+6
| | | | | Cc: [email protected] Reviewed: Marek Olšák <[email protected]>
* swr: fix transform feedback logicGeorge Kyriazis2017-07-274-8/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The shader that is used to copy vertex data out of the vs/gs shaders to the user-specified buffer (streamout or SO shader) was not using the correct offsets. Adjust the offsets that are used just for the SO shader: - Make sure that position is handled in the same special way as in the vs/gs shaders - Use the correct offset to be passed in the core - consolidate register slot mapping logic into one function, since it's been calculated in 2 different places (one for calcuating the slot mask, and one for the register offsets themselves Also make room for all attibutes in the backend vertex area. Fixes: - all vtk GL2PS tests - 18 piglit tests (16 ext_transform_feedback tests, arb-quads-follow-provoking-vertex and primitive-type gl_points v2: - take care of more SGV slots in slot mapping logic - trim feState.vsVertexSize - fix GS interface and incorporate GS while calculating vsVertexSize Note that vsVertexSize is used in the core as the one parameter that controls vertex size between all stages, so it has to be adjusted appropriately for the whole vs/gs/fs pipeline. Also note that GS and SO is not fully implemented. This will be addressed later. fixes: - fixes total of 20 piglit tests CC: 17.2 <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: non-regex knob fallback code for gcc < 4.9Tim Rowley2017-07-271-0/+21
| | | | | | | | gcc prior to 4.9 didn't implement <regex>, causing a startup crash in the swr knob parameter reading code. CC: <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
* mesa: check that buffer object is not NULL before initializing itTimothy Arceri2017-07-271-4/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: small builtin inline tidy upTimothy Arceri2017-07-271-4/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* virgl: encode index buffer offset.Dave Airlie2017-07-271-1/+1
| | | | | | | Fixes arb_vertex_buffer_object-combined-vertex-index Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: Fix inversed test in st_api_destroy_drawableMichel Dänzer2017-07-271-1/+1
| | | | | | | | | | Fixes a drawable leak. Fixes: bbc29393d3be ("st/mesa: create framebuffer iface hash table per st manager") Bugzilla: https://bugs.freedesktop.org/101930 Tested-by: Nick Sarnie <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radv/ac: port SI TC L1 write corruption fix.Dave Airlie2017-07-261-3/+5
| | | | | | | | | This ports 72e46c988 to radv. radeonsi: apply a TC L1 write corruption workaround for SI Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/winsys: fix padding command stream for SIDave Airlie2017-07-261-4/+6
| | | | | | | | We were adding pad to size after creating the object, so we could submit a CS bigger than the bo created for it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: realign SI workaround with radeonsi.Dave Airlie2017-07-261-2/+3
| | | | | | | | | | | | This ports: da7453666ae radeonsi: don't apply the Z export bug workaround to Hainan to radv. Just noticed in passing. Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/clear: Don't perform redundant depth clearsJason Ekstrand2017-07-261-3/+31
| | | | | | | | | | | | | | | We already have this little optimization for color clears. Now that we're actually tracking whether or not a slice has any fast-clear blocks, it's easy enough to add for depth clears too. Improves performance of GFXBench 4 TRex at 1920x1080 by: - Skylake GT4: 0.905932% +/- 0.0620197% (n = 30) - Apollolake: 0.382434% +/- 0.1134730% (n = 25) v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're no longer necessary (other patches already landed to do that part) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Only do depth resolves prior to clearing when neededJason Ekstrand2017-07-261-3/+36
| | | | | | | | | | | | | | | | | | | When changing the clear value, we need to resolve any fast cleared data. Previously, we were performing resolves on every slice with HiZ enabled. We only need to resolve slices that a) have fast clear data, and b) aren't about to be cleared to the new color. In the latter case, we were actually doing a resolve, and then a fast clear - when we could skip both, causing the existing fast cleared area to be updated to the new clear value for no additional work. This patch stops using intel_miptree_prepare_access in favor of a more optimal open coded loop that knows about our clear operation. v2: (by Ken) Rebase on islification, write a real commit message. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.Kenneth Graunke2017-07-262-5/+8
| | | | | | I want to use it in brw_clear.c. Reviewed-by: Lionel Landwerlin <[email protected]>
* ac/surface: fix hybrid graphics where APU=GFX9, dGPU=olderMarek Olšák2017-07-261-0/+12
| | | | | | | | v2: don't do it for compressed textures (bpp = 0) Cc: 17.2 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: decrease the number of compiler threadsMarek Olšák2017-07-262-3/+8
| | | | | Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: make S_FIXED function signed and move it to shared codeMarek Olšák2017-07-263-9/+5
| | | | | | | | | | | This fixes a bug uncovered by: 2412c4c81ea0488df865817a0de91ec46e359b72 util: Make CLAMP turn NaN into MIN. Cc: 17.2 <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: also clamp and quantize per-unit lod biasMarek Olšák2017-07-263-4/+6
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: fix unconditional return in st_framebuffer_iface_removeMarek Olšák2017-07-261-1/+1
| | | | | | | Noticed by James Legg @ Feral. Cc: 17.2 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* drirc: whitelist glthread for Mount and Blade WarbandMarek Olšák2017-07-261-0/+3
| | | | | From 25-26 min fps to 31, used the game in conjuction with a mod (full invasion 2) beaumaris castle map and 200 bots.
* egl: move KHR_no_error vs debug/robustness check further downGrigori Goronzy2017-07-261-11/+10
| | | | | | | | | | | | We'll fail to flag an error if the context flags appear after the no-error attribute in the context attribute list. Delay the check to after attribute parsing to fix this. Fixes: 4909519a665 ("egl: Add EGL_KHR_create_context_no_error support") Cc: [email protected] [Emil Velikov: add fixes/stable tags, commit message polish] Reviewed-by: Emil Velikov <[email protected]>
* radv: rename physical_device->uuid[] to cache_uuid[]Andres Rodriguez2017-07-263-5/+5
| | | | | | | We have a few UUIDs, so lets be more specific. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+Nicolai Hähnle2017-07-261-15/+24
| | | | | | | | | The number of supported waves per thread group has been reduced to 16 with gfx9. Trying to use 32 waves causes hangs, and barriers might not work correctly with > 16 waves. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix detection of DRAW_INDIRECT_MULTI on SINicolai Hähnle2017-07-261-2/+2
| | | | | | | | | | | | | | | | The firmware version numbers for SI were wrong. The new numbers are probably too conservative (we don't have a definitive answer by the firmware team), but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on Tahiti (by Gustaw) and on Verde (by myself). While this is technically adding a feature, it's a feature we thought we had for a long time. The change is small enough and we're early enough in the 17.2 release cycle that it should still go in. Reported-by: Gustaw Smolarczyk <[email protected]> Cc: 17.2 <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* anv: only expose up to 28 vertex attributesIago Toral Quiroga2017-07-261-1/+1
| | | | | | | | | | | | The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs. However, the maximum allowed value of "Vertex URB Entry Read Length" in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements. Because we also need to reserve a vertex buffer to upload VertexIndex/InstanceIndex and another to upload DrawID when needed, we can only expose 28. Cc: "17.2" <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/cmd_buffer: fix off by one error in assertionIago Toral Quiroga2017-07-261-1/+1
| | | | | Cc: "17.2" <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Shut up Coverity warning about HiZ buffers.Kenneth Graunke2017-07-251-0/+1
| | | | | | | | Here the AUX_USAGE_* mode indicates that we have HiZ, so we will have a HiZ buffer. But Coverity doesn't know that, so it thinks it might be NULL because we checked hiz_buf != NULL earlier. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix = vs == in MCS aux usage assert.Kenneth Graunke2017-07-251-1/+1
| | | | | | | Caught by Coverity (CID 1415680). Cc: "17.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix offset addition in get_isl_surf.Kenneth Graunke2017-07-251-3/+3
| | | | | | | | | Increase the value, not the pointer to the stack variable. Caught by Coverity (CID 1415574). Not shipped in a real release. Cc: "17.2" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa/st: fix inconsistent indentation of st_cb_bufferobjects.cAndres Rodriguez2017-07-261-18/+18
| | | | | | | No changes, just re-indent. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* compiler: move glsl_interface_packing enum to shader_enums.hTimothy Arceri2017-07-264-27/+11
| | | | | | This allows us to drop the duplicate gl_uniform_block_packing enum. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa/st: fix unused variable warningsTimothy Arceri2017-07-264-10/+11
| | | | | Reviewed-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/st: move st_pipe_format_to_mesa_format() call to where its usedTimothy Arceri2017-07-261-2/+1
| | | | | Reviewed-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: fix unused variable warningTimothy Arceri2017-07-261-3/+5
| | | | | Reviewed-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: drop useless assertTimothy Arceri2017-07-261-1/+0
| | | | | | | NewBufferObj() is called when the shared state is allocated so we wouldn't get this far if it was NULL. Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: call binding functions directly from glDeleteBuffersTimothy Arceri2017-07-261-3/+9
| | | | | | This avoids useless error checking. Reviewed-by: Samuel Pitoiset <[email protected]>
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