aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* ci: Enable pre-merge fractional vulkan CTS runs on the turnip driver.Eric Anholt2020-06-094-0/+130
* ci: Build the full VK CTS for baremetal testing.Eric Anholt2020-06-096-10/+40
* ci: Disable shader cache on vulkan CI runs.Eric Anholt2020-06-091-0/+5
* ci: Bump up to the current version of the VK CTS.Eric Anholt2020-06-092-3/+8
* turnip: Fix crashes in compute with no descriptors to load.Eric Anholt2020-06-091-1/+3
* frontends/vdpau: Default destination rect to source rectThong Thai2020-06-091-0/+3
* radeonsi: require LLVM 11 for gfx10.3Marek Olšák2020-06-091-0/+6
* radeonsi: add support for Sienna CichlidMarek Olšák2020-06-096-2/+19
* ac: align num_vgprs for gfx10.3Marek Olšák2020-06-096-5/+23
* radeonsi: don't set any XNACK options on gfx10.3Marek Olšák2020-06-092-4/+4
* radeonsi: set BIG_PAGE fields on gfx10.3Marek Olšák2020-06-092-3/+23
* radeonsi: move L2_CACHE_CONTROL registers into si_emit_framebuffer_stateMarek Olšák2020-06-091-29/+32
* radeonsi: implement R9G9B9E5 render target and image store support on gfx10.3Marek Olšák2020-06-094-9/+51
* radeonsi: enable larger SDMA clears and copies on gfx10.3Marek Olšák2020-06-092-8/+15
* radeonsi: honor a user-specified pitch on gfx10.3Marek Olšák2020-06-091-6/+20
* ac/surface: add displayable DCC code for gfx10.3Marek Olšák2020-06-091-7/+20
* ac,radeonsi: start adding support for gfx10.3Marek Olšák2020-06-098-17/+64
* ac,radeonsi: replace == GFX10 with >= GFX10 where it's neededMarek Olšák2020-06-093-9/+12
* radeonsi: enable ARB_sparse_bufferMarek Olšák2020-06-091-4/+1
* tu: Fix context faults loading unused descriptor setsConnor Abbott2020-06-093-0/+28
* i965: Work around incorrect usage of glDrawRangeElements in UE4Danylo Piliaiev2020-06-091-0/+20
* tu: Rewrite flushing to use barriersConnor Abbott2020-06-094-154/+1049
* tu: Remove useless event_write helpersConnor Abbott2020-06-091-19/+7
* tu: Don't actually track seqno's for eventsConnor Abbott2020-06-094-76/+78
* tu: Remove useless post-binning flushesConnor Abbott2020-06-091-25/+9
* panfrost: Mark PIPE_BUFFER BOs as not renderableIcecream952020-06-091-1/+2
* winsys/radeon: do not cast bo->va as void*Pierre-Eric Pelloux-Prayer2020-06-093-11/+11
* ci: use separate docker images for baremetal buildsChristian Gmeiner2020-06-096-178/+54
* ci: add arm_test-base docker imageChristian Gmeiner2020-06-094-61/+189
* radv/llvm: expose VK_EXT_shader_demote_to_helper_invocation with LLVM 9+Samuel Pitoiset2020-06-094-3/+4
* glthread: sync in glFlush for multiple contextsMarek Olšák2020-06-091-1/+7
* gallium/u_vbuf: add a faster path for uploading non-interleaved attribsMarek Olšák2020-06-091-34/+83
* gallium/u_vbuf: get rid of some pointer dereferencesMarek Olšák2020-06-091-9/+11
* nir: use bitfield_insert instead of bfi in nir_lower_double_opsBen Skeggs2020-06-091-1/+3
* turnip: fix VFD_CONTROL for binning passJonathan Marek2020-06-081-1/+1
* turnip: use common emit_xs_cntl to fill a6xx_sp_xs_ctrl_reg0Jonathan Marek2020-06-081-28/+28
* turnip: fix HW binning with geometry shaderJonathan Marek2020-06-081-2/+6
* turnip: correctly emit non-binning vs in transform feedback caseJonathan Marek2020-06-081-3/+5
* freedreno/a6xx: use nonbinning VS when GS is usedJonathan Marek2020-06-081-4/+5
* turnip: clamp sampler minLod/maxLodJonathan Marek2020-06-081-2/+4
* turnip: update some properties based on blob driverJonathan Marek2020-06-081-8/+8
* turnip: move HLSQ_UPDATE_CNTL write to before xs config writesJonathan Marek2020-06-081-3/+3
* nir: Fix logic that ends combine barrier sequenceCaio Marcelo de Oliveira Filho2020-06-081-1/+1
* intel/fs: Add Fall-through commentCaio Marcelo de Oliveira Filho2020-06-081-0/+1
* spirv: Memory semantics is optional for OpControlBarrierCaio Marcelo de Oliveira Filho2020-06-081-9/+9
* nir: Fix printing execution scope of a scoped barrierCaio Marcelo de Oliveira Filho2020-06-081-1/+4
* etnaviv: drop translate_blend(..)Christian Gmeiner2020-06-082-22/+9
* glsl: inline functions with unsupported return type before converting to nirDanylo Piliaiev2020-06-081-0/+6
* aco: use v_xor3_b32Rhys Perry2020-06-081-0/+3
* ac/gpu_info, radv: set max_wave64_per_simd to 20 on GFX10Rhys Perry2020-06-082-4/+12
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 00:33:32 +0000