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* st/mesa: avoid integer overflows with buffers >= 512MBIlia Mirkin2015-09-171-2/+2
| | | | | | | | | | This fixes failures with the newly-submitted max-size texture buffer piglit test for GPUs exposing >= 128M max texels. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> (cherry picked from commit eb081681df248750727a8a76436760d617b4a6a9)
* gbm: convert gbm bo format to fourcc format on dma-buf importRay Strode2015-09-171-1/+17
| | | | | | | | | | | | | | | | | | | | | | At the moment if a gbm buffer is imported and the gbm buffer has an old-style GBM_BO_FORMAT format, the import will crash, since it's passed directly to DRI functions that expect a fourcc format (as provided by the newer GBM_FORMAT definitions) This commit addresses the problem in two ways: 1) it prevents invalid formats from leading to a crash by returning EINVAL if the image couldn't be created 2) it translates GBM_BO_FORMAT formats into the comparable GBM_FORMAT formats. Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531 CC: "10.6 11.0" <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> (cherry picked from commit 4bf151e66279da00655cec02aadb52c9c6583213)
* i965/vec4: Fix saturation errors when coalescing registersAntia Puentes2015-09-171-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the register types do not match and the instruction that contains the final destination is saturated, register coalescing generated non-equivalent code. This did not happen when using IR because types usually matched, but it is visible in nir-vec4. For example, mov vgrf7:D vgrf2:D mov.sat m4:F vgrf7:F is coalesced to: mov.sat m4:D vgrf2:D The patch prevents coalescing in such scenario, unless the instruction we want to coalesce into is a MOV (without type conversion implied). In that case, the patch sets the register types to the type of the final destination. Shader-db results in HSW (only vec4 instructions shown): total instructions in shared programs: 1754415 -> 1754416 (0.00%) instructions in affected programs: 74 -> 75 (1.35%) helped: 0 HURT: 1 GAINED: 0 LOST: 0 Only one extra instruction in one of the shaders, that comes from eliminating a saturation error by preventing register coalesce. Cc: "10.6 11.0" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 79f1a7ae28c37f77e08e550cd077959a2a1f8341)
* i965/vec4: Don't reswizzle hardware registersJason Ekstrand2015-09-171-0/+8
| | | | | | | Cc: "11.0 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91719 Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 1037e0a84f61f4b1815093bcfd548d4b58ca106f)
* nvc0: remove BGRA4 format supportIlia Mirkin2015-09-171-0/+2
| | | | | | | | | | | | Something is wrong with the support somewhere. I couldn't get the blob driver to use it either, although it happily used RGB5_A1. teximage-colors works, but WoW seems to fail in the menus for drawing text. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 342e68dc60eebb20ac1be9f47800ee9e604354f0)
* nv30: Disable msaa unless requested from the env by NV30_MAX_MSAAHans de Goede2015-09-172-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Some modern apps try to use msaa without keeping in mind the restrictions on videomem of older cards. Resulting in dmesg saying: [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12 Because we are running out of video memory, after which the program using the msaa visual freezes, and eventually the entire system freezes. To work around this we do not allow msaa visauls by default and allow the user to override this via NV30_MAX_MSAA. Signed-off-by: Hans de Goede <[email protected]> [imirkin: move env var lookup to screen so that it's only done once] Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 3e9df0e3af7a8a84147ae48f588e9c435bf65b98) Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/gallium/drivers/nouveau/nv30/nv30_screen.c
* nvc0: always emit a full shader colormaskIlia Mirkin2015-09-171-1/+1
| | | | | | | | | | | | | | | Indications are that if the colormask indicates a single bit set on fermi, that value will always be read from $r0 instead of a potentially higher register (if e.g. green is set). Not to upset the counting logic, always set the header up with a full color mask for each RT. Such a situation can basically only ever happen with generated blit shaders. Fixes the following piglit on Fermi (Kepler is unaffected): fbo-stencil blit GL_DEPTH32F_STENCIL8 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 39df725f731f75f488c75a4910169beb352213fb)
* nv30: Fix max width / height checks in nv30 sifm codeHans de Goede2015-09-171-2/+2
| | | | | | | | | | | | | | | | | | The sifm object has a limit of 1024x1024 for its input size and 2048x2048 for its output. The code checking this was trying to be clever resulting in it seeing a surface of e.g 1024x256 being outside of the input size limit. This commit fixes this. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 87073c69f3e253044bc235f34917aaa89041a63c) Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/gallium/drivers/nouveau/nv30/nv30_transfer.c
* st/mesa: don't fall back to 16F when 32F is requestedIlia Mirkin2015-09-171-14/+8
| | | | | | | | | | | | Nothing in the spec allows for the reduced precision, and this also fixes st_QuerySamplesForFormat for nv50, which does not allow MS8 on RGBA32F. Now this will be respected instead of reporting MS8 as supported with an assumption that the format used will be RGBA16F. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit e40f32d5626c87d9e77bbc261df3648cd54bd066)
* llvmpipe: convert double to long long instead of unsigned long longOded Gabbay2015-09-171-1/+1
| | | | | | | | | | | | | | | | | | round(val*dscale) produces a double result, as val and dscale are double. However, LLVMConstInt receives unsigned long long, so there is an implicit conversion from double to unsigned long long. This is an undefined behavior. Therefore, we need to first explicitly convert the round result to long long, and then let the compiler handle conversion from that to unsigned long long. This bug manifests itself in POWER, where all IMM values of -1 are being converted to 0 implicitly, causing a wrong LLVM IR output. Signed-off-by: Oded Gabbay <[email protected]> CC: "10.6 11.0" <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> (cherry picked from commit 4f2290d1612569686284609059d29a85c9de67cf)
* nv30: Implement color resolve for msaaHans de Goede2015-09-172-14/+8
| | | | | | | | | | | | Note this is not ideal. Since the sifm can only do source sizes upto 1024x1024 we end up using the blitter on nv4x, which is not that fast. And on nv3x we end up using the cpu which is really slow. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit 3c6c4d4f298ec81fe57992790a68aaab2e573519)
* nv30: Fix creation of scanout buffersHans de Goede2015-09-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | Scanout buffers on nv30 must always be non-swizzled and have special width alignment constraints. These constrains have been taken from the xf86-video-nouveau src/nv_accel_common.c: nouveau_allocate_surface() function. nouveau_allocate_surface() applies these width constraints only when a tiled attribute is set, which it sets for all surfaces allocated via dri, and this "tiling" is not the same as swizzling, scanout surfaces must be linear / have a uniform_pitch or only complete garbage is shown. This commit fixes dri3 on nv30 showing a garbled display, with dri3 the scanout buffers are allocated by mesa, rather then by the ddx, and the wrong stride of these buffers was causing the garbled display. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit 3329703eb116a7ad73bc694356b43e014532240b)
* mesa: Don't allow wrong type setters for matrix uniformsIan Romanick2015-09-171-0/+25
| | | | | | | | | | | | | | Previously we would allow glUniformMatrix4fv on a dmat4 and glUniformMatrix4dv on a mat4. Both are illegal. That later also overwrites the storage for the mat4 and causes bad things to happen. Should fix the (new) arb_gpu_shader_fp64-wrong-type-setter piglit test. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: Dave Airlie <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 7237c937af3b495191bee2f7240901e3a9daf1fb)
* mesa: Pass the type to _mesa_uniform_matrix as a glsl_base_typeIan Romanick2015-09-173-42/+42
| | | | | | | | | | | | | This matches _mesa_uniform, and it enables the bug fix in the next patch. v2: s/type/basicType/ in the assert in _mesa_uniform_matrix. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> [v1] Cc: Dave Airlie <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit a6976f09727014730f45ec27c714c6a8140e074a)
* cherry-ignore: add commit non applicable for 10.6Emil Velikov2015-09-171-0/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallivm: Workaround LLVM PR23628.Jose Fonseca2015-09-171-0/+11
| | | | | | | | | | | | | Temporarily undefine DEBUG macro while including LLVM C++ headers, leveraging the push/pop_macro pragmas, which are supported both by GCC and MSVC. https://bugs.freedesktop.org/show_bug.cgi?id=90621 Trivial. (cherry picked from commit 09d6243aed016eed4518435c9885275dbb6d2aa9) Nominated-by: Sedat Dilek <[email protected]>
* gallivm: Do not use NoFramePointerElim with LLVM 3.7.Vinson Lee2015-09-172-0/+4
| | | | | | | | | | | TargetOptions::NoFramePointerElim was removed in llvm-3.7.0svn r238244 "Remove NoFramePointerElim and NoFramePointerElimOverride from TargetOptions and remove ExecutionEngine's dependence on CodeGen. NFC." Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Tom Stellard <[email protected]> (cherry picked from commit 147ffd48166d851341cadd12de98895f32ec25a2) Nominated-by: Sedat Dilek <[email protected]>
* i965: Momentarily pretend to support ARB_texture_stencil8 for blits.Kenneth Graunke2015-09-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell's stencil blitting code attempts to bind a renderbuffer as a texture, using dd->BindRenderbufferTexImage(). This calls _mesa_init_teximage_fields(), which then attempts to set img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which assert fails if internalFormat is GL_STENCIL_INDEX8 but ARB_texture_stencil8 is unsupported. To work around this, just pretend to support the extension momentarily, during the blit. Meta has already munged a variety of other things in the context (including the API!), so it's not that much worse than what we're already doing. Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47 (mesa/teximage: use correct extension for accept stencil texture.). v2: Add an XXX comment explaining the situation (requested by Jason Ekstrand and Martin Peres), and an assert that we don't support the extension so we remember to remove this hack (requested by Neil Roberts). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit f83b9e58f6e8a748def367c7d523eb7285b1aeb7) Nominated-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 10.6.7Emil Velikov2015-09-101-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add release notes for 10.6.7mesa-10.6.7Emil Velikov2015-09-101-0/+74
| | | | Signed-off-by: Emil Velikov <[email protected]>
* Update version to 10.6.7Emil Velikov2015-09-101-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* glsl: Handle attribute aliasing in attribute storage limit check.Kenneth Graunke2015-09-101-28/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | In various versions of OpenGL and GLSL, it's possible to declare multiple VS input variables with aliasing attribute locations. So, when computing the storage requirements for vertex attributes, we can't simply add up the sizes. Instead, we need to look at the enabled slots. This patch begins tracking which attributes are double types that are larger than 128-bits (i.e. take up two vec4 slots). We then count normal attributes once, and count the double-size attributes a second time. Fixes deQP functional.attribute_location.bind_aliasing.max_cond_* tests on i965, which regressed with commit ad208d975a6d3aebe14f7c2c16039ee20. No Piglit changes on llvmpipe (which actually supports dvecs). Cc: "10.6 11.0" <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> (cherry picked from commit c3294ca5a13cf3f0eb3d9907a46ff8ce4bc2963b)
* mesa/teximage: use correct extension for accept stencil texture.Dave Airlie2015-09-101-1/+1
| | | | | | | | | | | | | | | This was using the wrong extension, ARB_stencil_texturing doesn't mention any changes in this area. Fixes "dEQP-GLES3.functional.fbo.completeness.renderable.texture. stencil.stencil_index8." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90751 Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit f7aad9da20b13c98f77d6a690b327716f39c0a47) Nominated-by: Mark Janes <[email protected]>
* Revert "i965: Momentarily pretend to support ARB_texture_stencil8 for blits."Emil Velikov2015-09-101-7/+0
| | | | | | This reverts commit 6811df8d3510c35899e992bae82c063e20e62cc8. Erroneous nomination. See mailing list for details.
* docs: add sha256 checksums for 10.6.6Emil Velikov2015-09-041-1/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add release notes for 10.6.6mesa-10.6.6Emil Velikov2015-09-041-0/+163
| | | | Signed-off-by: Emil Velikov <[email protected]>
* Update version to 10.6.6Emil Velikov2015-09-041-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* i965: Momentarily pretend to support ARB_texture_stencil8 for blits.Kenneth Graunke2015-09-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell's stencil blitting code attempts to bind a renderbuffer as a texture, using dd->BindRenderbufferTexImage(). This calls _mesa_init_teximage_fields(), which then attempts to set img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which assert fails if internalFormat is GL_STENCIL_INDEX8 but ARB_texture_stencil8 is unsupported. To work around this, just pretend to support the extension momentarily, during the blit. Meta has already munged a variety of other things in the context (including the API!), so it's not that much worse than what we're already doing. Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47 (mesa/teximage: use correct extension for accept stencil texture.). v2: Add an XXX comment explaining the situation (requested by Jason Ekstrand and Martin Peres), and an assert that we don't support the extension so we remember to remove this hack (requested by Neil Roberts). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit f83b9e58f6e8a748def367c7d523eb7285b1aeb7) Nominated-by: Mark Janes <[email protected]>
* mesa: add GL_RED, GL_RG support for floating point texturesTapani Pälli2015-09-041-3/+34
| | | | | | | | | | | | | | | | | | | Mesa supports EXT_texture_rg and OES_texture_float. This patch adds support for using unsized enums GL_RED and GL_RG for floating point targets and writes proper checks for internalformat when format is GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT. Later, internalformat will get adjusted by adjust_for_oes_float_texture after these checks. v2: simplify to check vs supported enums v3: follow the style and break out if internalFormat ok (Kenneth) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748 Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 5b0d6f5c1bc3f7bd37c6efebf48f80ca6ff3ef87) Nominated-by: Mark Janes <[email protected]>
* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-09-041-5/+1
| | | | | | | | | | | | | | | This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043. The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4. interpolation.lines_wide" test appears to be broken on Cherryview when we expose line widths greater than 12.0. I'm not sure why. For now, just go back to the limits we used on older platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902 Acked-by: Matt Turner <[email protected]> (cherry picked from commit 16658f426dbd81fcbc317b21ae9a3f7c9b6448fb) Nominated-by: Mark Janes <[email protected]>
* i965: Fix copy propagation type changes.Kenneth Graunke2015-09-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | commit 472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693 introduced code to change the types of SEL and MOV instructions for moves that simply "copy bits around". It didn't account for type conversion moves, however. So it would happily turn this: mov(8) vgrf6:D, -vgrf5:D mov(8) vgrf7:F, vgrf6:UD into this: mov(8) vgrf6:D, -vgrf5:D mov(8) vgrf7:D, -vgrf5:D which erroneously drops the conversion to float. Cc: "11.0 10.6" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 2ace64fd598816fd1be9877962734242fc27b87b)
* i965/fs: Handle MRF destinations in lower_integer_multiplication().Matt Turner2015-09-041-4/+4
| | | | | | | | | | | | | | | | | The lowered code reads from the destination, which isn't possible from message registers. Fixes the following dEQP tests on SNB: dEQP-GLES3.functional.shaders.precision.int.highp_mul_fragment dEQP-GLES3.functional.shaders.precision.int.mediump_mul_fragment dEQP-GLES3.functional.shaders.precision.int.lowp_mul_fragment Cc: "10.6 11.0" <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 9390cb84593bda516e8c1521c87a08475574d1be)
* radeonsi: fix a Unigine Heaven hang when drirc is missingMarek Olšák2015-09-024-1/+29
| | | | | | | | | | | Cc: 10.6 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> (cherry picked from commit 9b510a9652297a63677f1d55b2bf444694fd94e1) Conflicts: src/gallium/drivers/radeonsi/si_shader.h src/gallium/drivers/radeonsi/si_state_shaders.c
* r600g: fix calculation for gpr allocationDave Airlie2015-09-021-1/+1
| | | | | | | | | | | | | | | | I've been chasing a geom shader hang on rv635 since I wrote r600 geom code, and finally I hacked some values from fglrx in and I could run texelfetch without failures. This is totally my fault as well, maths fail 101. This makes geom shaders on r600 not fail heavily. Cc: "10.6" "11.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 0de53ccc8cbee0f63ba25c9e72664b3cbd31be54)
* r600/sb: update last_cf for finalize if.Dave Airlie2015-09-021-0/+3
| | | | | | | | | | | | | As Glenn did for finalize_loop we need to update_cf when we add a POP at the end of a shader. I think this fixes one of the earlier shader going off end of memory problems we've stopped. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.6" "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 3063913f77cd2db1a263cb824a5c8c3dcc1a51a0)
* mesa: add missing queries for ARB_direct_state_accessDaniel Scharrer2015-09-022-0/+98
| | | | | | | | | | | | | | | This adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and GL_SAMPLER_BINDING, as well as textue queries (glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET. CC: "10.6 11.0" <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Signed-off-by: Fredrik Höglund <[email protected]> (cherry picked from commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8) Conflicts: src/mesa/main/texparam.c
* mesa: only copy the requested teximage facesIlia Mirkin2015-09-021-2/+2
| | | | | | | | | | | | | | | Cube maps are special in that they have separate teximages for each face. We handled that by copying the data to them separately, but in case zoffset != 0 or depth != 6 we would read off the end of the client array or modify the wrong images. zoffset/depth have already been verified by the time the code gets to this stage, so no need to double-check. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 2259b111003f2e8c55cae42677ec45345fb1b6e3)
* i965/fs: Split VGRFs after lowering pull constantsJason Ekstrand2015-09-021-2/+2
| | | | | | | | | | | The split_virtual_grfs code doesn't properly rewrite reladdr so we need to make sure that any uniform indirects are lowered away first. This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit Cc: "10.6" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit fee0c5af11dd0995de96e7053377d425a66d03a0)
* mesa: create multisample fallback textures like normal texturesMarek Olšák2015-09-021-0/+2
| | | | | | | | | | This works if drivers upsample on upload (like all radeon ones do). The alternative is an unexpected GL error from anything calling _mesa_update_state and possibly other issues. Cc: 10.6 11.0 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit f432ae899fb81468778dbeb17ac7615da3ed5c0d)
* mesa: enable texture stencil8 for multisampleDave Airlie2015-09-021-2/+5
| | | | | | | | | | This fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44 from the ogl conform suite. Reviewed-by: Ilia Mirkin <[email protected]> Cc: 10.6 11.0 <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f)
* i965: Always re-emit the pipeline select during invariant state emissionChris Wilson2015-09-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the older platforms where we don't have logical contexts preserving state across batches, we emit the invariant state setup on every batch using the brw_invariant_state atom. This includes the pipeline selection which is cached with the introduction of commit 0e0e23ef537c9add672ff322f34e129a07edc55e Author: Jordan Justen <[email protected]> Date: Wed Apr 22 11:43:50 2015 -0700 i965/state: Emit pipeline select when changing pipelines However, we do not reset the cache between batches on context-less platforms resulting in us not setting the pipeline selection and can cause GPU hangs if a media pipelined was loaded in the meantime (e.g. mixing mplayer/gstreamer using libva and gnome-shell). A simple solution is to just forcibly re-emit the pipeline select along with the invariant state and reset the cache at that point. Reported-and-tested-by: Tomasz C. <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254 Signed-off-by: Chris Wilson <[email protected]> Cc: Jordan Justen <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 4e5752e2b78243a71766538f62ca0a80488047a7)
* glsl: create program resource list after LinkShaderTapani Pälli2015-09-022-4/+2
| | | | | | | | | | Resource list can be created properly only after LinkShader hook has been called to make sure all dead variables have been removed. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925 (cherry picked from commit f045b8b2ff5ac75da3e092f482fd1717571d8462)
* glsl: expose build_program_resource_list functionTapani Pälli2015-09-022-1/+5
| | | | | | | | | This is required so that we can move resource list creation to happen later. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> (cherry picked from commit 73afa31f07fe4af605088f6590edc4227652c482)
* glsl: build stageref mask using IR, not symbol tableTapani Pälli2015-09-021-3/+11
| | | | | | | | | | Instead of using symbol table, build mask by inspecting IR. This change is required by further patches to move resource list creation to happen later when symbol table does not exist anymore. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> (cherry picked from commit ccaf37f4496eb836866c9daacf21f1f5ac8c6d66)
* mesa/readpixels: check strides are equal before skipping conversionDave Airlie2015-09-021-1/+2
| | | | | | | | | | | | | | The CTS packed_pixels test checks that readpixels doesn't write into the space between rows, however we fail that here unless we check the format and stride match. This fixes all the core mesa problems with CTS packed_pixels tests. Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 32769ac016dee4ce5767a922f91de47df4ce984d)
* texcompress_s3tc/fxt1: fix stride checks (v1.1)Dave Airlie2015-09-022-5/+5
| | | | | | | | | | | | | | | | | | | The fastpath currently checks the RowLength != width, but if you have a RowLength of 7, and Alignment of 4, then that shouldn't match. align the rowlength to the pack alignment before comparing. This fixes compressed cases in CTS packed_pixels_pixelstore test when SKIP_PIXELS is enabled, which causes row length to get set. v1.1: add fxt1 fix (Iago) Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit b4a70401f52e5d7e08c94715b250ea1de8f63d15)
* st/readpixels: fix accel path for skipimages.Dave Airlie2015-09-021-2/+2
| | | | | | | | | | | | | | | We don't need to use the 3d image address here as that will include SKIP_IMAGES, and we are only blitting a single 2D anyways, so just use the 2D path. This fixes some memory overruns under CTS packed_pixels.packed_pixels_pixelstore when PACK_SKIP_IMAGES is used. Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 6a3e1fb958778e00e8fe2d860b6327fc4409c148)
* i965: Prevent coordinate overflow in intel_emit_linear_blitChris Wilson2015-09-021-36/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes regression from commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1 Author: Kenneth Graunke <[email protected]> Date: Wed Apr 15 03:04:33 2015 -0700 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. which adjusted the coordinates to be relative to the nearest cacheline. However, this then offsets the coordinates by up to 63 and this may then cause them to overflow the BLT limits. For the well aligned large transfer case, we can use 32bpp pixels and so reduce the coordinates by 4 (versus the current 8bpp pixels). We also have to be more careful doing the last line just in case it may exceed the coordinate limit. Reported-and-tested-by: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Anuj Phogat <[email protected]> Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit d38a5601068ae1d923efece8f28757777f4474e4) [Emil Velikov: drop the extra INTEL_MIPTREE_TRMODE_NONE arguments] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/mesa/drivers/dri/i965/intel_blit.c
* gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packetsMarek Olšák2015-09-021-8/+8
| | | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit 437cb1e3f482570447501526927df4d80c845bf5)
* r600g/sb: Don't crash on empty if jump targetGlenn Kennard2015-09-021-1/+4
| | | | | | | Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b)
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