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* st/dri: remove GALLIUM_MSAA and __GL_FSAA_MODE environment variablesMarek Olšák2014-09-191-35/+0
| | | | | | | | | | | | | | | | | | | | Some users don't understand that these variables can break OpenGL. The general is rule is that if an app supports MSAA, you mustn't use GALLIUM_MSAA. For example, if an app has an 8xMSAA FBO and GALLIUM_MSAA=4 is set, resolving the FBO to the back buffer will be rejected which will look like this on all gallium drivers: http://www.phoronix.com/scan.php?page=article&item=amd_radeonsi_msaa The environment variables also have no effect on modern apps like TF2, but there is still a performance hit due to wasted bandwidth and VRAM. In a nutshell, it does more harm than good. Cc: 10.2 10.3 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* vc4: Fix perspective interpolation.Eric Anholt2014-09-191-1/+1
| | | | Fixes the mesa reflect demo and 6 tests under interpolation/
* vc4: Use the same method as for FRAG_Z to handle fragcoord W.Eric Anholt2014-09-195-13/+15
| | | | I need to get the non-reciprocal version of W for interpolation, anyway.
* util: don't try to emit half-float intrinsics if avx isn't availableRoland Scheidegger2014-09-191-1/+1
| | | | | | | | | These instructions only have vex encodings, thus they can't be used without avx. (Technically, one can still use avx-128 if avx isn't available because the environment doesn't store the ymm registers, however I don't think llvm can.) Reviewed-by: Jose Fonseca <[email protected]>
* i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layeredSamuel Iglesias Gonsalvez2014-09-192-3/+3
| | | | | | | | | | | | | | | | Geometry shaders was the only thing we needed to enable GLSL 1.50 and OpenGL 3.2 in gen6. v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth and Jordan realized that for this to work we also need GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be enabled before this patch), so we agreed to enable this together with OpenGL 3.2 in this patch. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Use a specific implementation of geometry shaders for gen6.Iago Toral Quiroga2014-09-191-20/+33
| | | | | | | | | | | | | In gen6 we will use the geometry shader implementation from gen6_gs_visitor.cpp and keep the implementation in brw_vec4_gs_visitor.cpp for gen7+. Notice that gen6_gs_visitor inherits from brw_vec4_gs_visitor so it is not a completely seprate implementation of geometry shaders. Also, gen6 does not support multiple dispatch modes, its default operation mode is equivalent to gen7's SINGLE mode, so select that in gen6 for consistency. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: upload ubo and pull constants surfaces.Iago Toral Quiroga2014-09-191-0/+2
| | | | | | | | | | | | Uniforms declared as uniform blocks are stored in ubo surfaces and need to be pulled from the geometry shader program so make sure we upload them first and do the same for pull constants. This fixes all piglit tests that use uniform blocks: bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-* Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable transform feedback support in geometry shadersSamuel Iglesias Gonsalvez2014-09-192-8/+11
| | | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Fix binding table clash between TF surfaces and textures.Iago Toral Quiroga2014-09-196-29/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | For gen6 geometry shaders we use the first BRW_MAX_SOL_BINDINGS entries of the binding table for transform feedback surfaces. However, vec4_visitor will setup the binding table so that textures use the same space in the binding table. This is done when calling assign_common_binding_table_offsets(0) as part if its run() method. To fix this clash we add a virtual method to the vec4_visitor hierarchy to assign the binding table offsets, so that we can change this behavior specifically for gen6 geometry shaders by mapping textures right after the first BRW_MAX_SOL_BINDINGS entries. Also, when there is no user-provided geometry shader, we only need to upload the binding table if we have transform feedback, however, in the case of a user-provided geometry shader, we can't only look into transform feedback to make that decision. This fixes multiple piglit tests for textureSize() and texelFetch() when these functions are called from a geometry shader in gen6, like these: bin/textureSize gs sampler2D -fbo -auto bin/texelFetch gs usampler2D -fbo -auto Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Avoid buffering transform feedback varyings twice.Iago Toral Quiroga2014-09-192-106/+83
| | | | | | | | | Currently we buffer transform feedack varyings separately. This patch makes it so that we reuse the values we have already buffered for all the output varyings of the geometry shader instead. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Buffer PSIZ/flags vertex data in gen6_gs_visitorSamuel Iglesias Gonsalvez2014-09-191-38/+41
| | | | | | | | | | | | | | Since geometry shaders can alter the value of varyings packed in the first output VUE slot (PSIZ), we need to buffer it together with all the other vertex data so we can emit the right value for each vertex when we do the URB writes. This fixes the following piglit test in gen6: tests/spec/glsl-1.50/execution/redeclare-pervertex-out-subset-gs.shader_test Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Setup SOL surfaces for user-provided geometry shadersSamuel Iglesias Gonsalvez2014-09-191-38/+81
| | | | | | | | | | Update gen6_gs_binding_table and gen6_sol_surface to use user-provided geometry program information when present. This is necessary to implement transform feedback support. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement transform feedback support in gen6_gs_visitorSamuel Iglesias Gonsalvez2014-09-193-45/+390
| | | | | | | | | | This takes care of generating code required to handle transform feedback. Notice that transform feedback isn't enabled yet, since that requires additional setups in other parts of the code that will come in later patches. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.Samuel Iglesias Gonsalvez2014-09-194-8/+19
| | | | | | | | | We will use this parameter in later patches to provide information relevant to transform feedback that needs to be set as part of the FF_SYNC message. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+46
| | | | | | | | | This opcode will be used when filling FF_SYNC header before emitting vertices and their data. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+33
| | | | | | | | | This opcode generates code to copy the specified destination index into subregister 5 of the MRF message header. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+63
| | | | | | | | | This opcode will be used when sending SVB WRITE messages to save transform feedback outputs into Streamed Vertex Buffers. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable texture units and upload sampler state.Iago Toral Quiroga2014-09-193-2/+3
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Assign geometry shader VUE map properly.Iago Toral Quiroga2014-09-192-7/+7
| | | | | | | | | | So far in gen6 we only used geometry shaders to implement transform feedback in vertex shaders, so we assumed that the VUE map for the geometry shader stage was always the same as for the vertex shader stage. This is no longer true now that we support user provided geometry shaders in gen6 too. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement support for gl_PrimitiveIdIn.Iago Toral Quiroga2014-09-192-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | For this we will need to move PrimitiveID information, delivered in the thread payload in r0.1, to a separate register (we use GS_OPCODE_SET_PRIMITIVE_ID for this), then map the corresponding varying slot to that register in the setup_payload() method. Notice that we cannot use a virtual register as the destination for the PrimitiveID because we need to map all input attributes to hardware registers in setup_payload(), which happens before virtual registers are mapped to hardware registers. We could work around that issue if we were able to compute the first non-payload register in emit_prolog() and move the PrimitiveID information to that register, but we can't because at that point we still don't know the final number uniforms that will be included in the payload. So, what we do is to place PrimitiveID information in r1, which is always delivered as part of the payload but its only populated with data relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE in the 3DSTATE_GS state packet. When we implement transform feedback, we wil make sure to move the value of r1 to another register before we overwrite it with the PrimitiveID. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.Iago Toral Quiroga2014-09-194-0/+27
| | | | | | | | | | In gen6 the geometry shader payload includes the PrimitiveID information in r0.1. When the shader code uses glPimitiveIdIn we will have to move this to a separate hardware register where we can map this attribute. This opcode takes the selected destination register and moves r0.1 there. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Handle the case where a geometry shader emits no output.Iago Toral Quiroga2014-09-192-122/+118
| | | | | | | | | | | | | | | | | | In gen6 we need to end the thread differently depending on whether we have emitted at least one vertex or not. In case we did, the EOT message must always include the COMPLETE flag or else the GPU hangs. If we have not produced any output, however, we can't use the COMPLETE flag. This would lead us to end the program with an ENDIF opcode, which we want to avoid (and actually is not permitted since it hits an assertion), so instead what we do is that we always request a new VUE handle every time we do an URB WRITE, even for the last vertex we emit. With this we make sure that whether we have emitted at least one vertex or none at all we have to finish the thread without writing to the URB, which works for both cases by setting the COMPLETE and UNUSED flags in the EOT message. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Make sure we complete the last primitive.Iago Toral Quiroga2014-09-191-0/+13
| | | | | | | | | Just in case the GS algorithm does not call EndPrimitive() for the last primitive produced. This is relevant only for non point outputs, since for this we are already setting the PrimEnd flag on each vertex we emit. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement geometry shaders for outputs other than points.Iago Toral Quiroga2014-09-192-7/+67
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add initial implementation for a gen6 geometry shader visitor.Iago Toral Quiroga2014-09-194-1/+415
| | | | | | | | | | | | Geometry shaders in gen6 are significantly different from gen7+ so it is better to have them implemented in a different file rather than adding gen6 branching paths all over brw_vec4_gs_visitor.cpp. This commit adds an initial implementation that only handles point output, which is the simplest case. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Generalize emit_urb_slot() to emit to any dst_reg.Iago Toral Quiroga2014-09-192-14/+20
| | | | | | | | | | In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Provide means to create registers of a given size.Iago Toral Quiroga2014-09-192-0/+15
| | | | | | | Implemented by Ilia Mirkin <[email protected]>. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.Iago Toral Quiroga2014-09-195-16/+10
| | | | | | | | | | We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be an immediate. In gen6 we need to set dword 2 of the URB write message header from values stored in separate register, so we need something more flexible. This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Upload binding table for user-provided geometry shaders.Iago Toral Quiroga2014-09-191-1/+4
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable URB space for user-provided geometry shaders.Iago Toral Quiroga2014-09-191-10/+20
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.Iago Toral Quiroga2014-09-192-33/+62
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add instruction URB flags to geometry shaders EOT message.Iago Toral Quiroga2014-09-191-1/+1
| | | | | | | | | Gen6 seems to require that EOT messages include the complete flag too or else the GPU hangs. We add will this flag to the instruction when we emit the thread end opcode. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.Iago Toral Quiroga2014-09-195-0/+42
| | | | | | | | | | | Gen6 geometry shaders need to allocate URB handles for each new vertex they emit after the first (the URB handle for the first vertex is obtained via the FF_SYNC message). This opcode adds the URB allocation mechanism to regular URB writes. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_FF_SYNC.Iago Toral Quiroga2014-09-195-0/+67
| | | | | | | | This implements the FF_SYNC message required in gen6 geometry shaders to get the initial URB handle. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gs: Reuse gen6 constant push buffers setup code in gen7+.Samuel Iglesias Gonsalvez2014-09-193-36/+7
| | | | | | | | The code required for gen6 and gen7+ is almost the same, so reuse it. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.Iago Toral Quiroga2014-09-193-33/+68
| | | | | Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Set brw->gs.enabled to FALSE in gen6_blorp_emit_gs_disable()Samuel Iglesias Gonsalvez2014-09-191-0/+1
| | | | | | | | See 7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c for more details. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_progSamuel Iglesias Gonsalvez2014-09-194-2/+16
| | | | | | | | | | | | | This is needed to support user-provided geometry shaders, since the brw_ff_gs_prog atom in gen6 only takes care of implementing transform feedback for vertex shaders. If there is no user-provided geometry shader the implementation falls back to the original code. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Skeleton for user GS program supportSamuel Iglesias Gonsalvez2014-09-191-35/+119
| | | | | | | | | | | | | | Currently, gen6 only uses geometry shaders for transform feedback so the state we emit is not suitable to accomodate general purpose, user-provided geometry shaders. This patch paves the way to add these support and the needed 3DSTATE_GS packet modifications for it. Previous code that emitted state to implement transform feedback in gen6 goes to upload_gs_state_adhoc_tf(). Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gs: Use single dispatch mode as fallback to dual object mode when possible.Iago Toral Quiroga2014-09-194-22/+36
| | | | | | | | | | | | | | | | | | Currently, when a geometry shader can't use dual object mode we fall back to dual instance mode, however, when invocations == 1, single dispatch mode is more performant and equally efficient in terms of register pressure. Single dispatch mode requires that the driver can handle interleaving of input registers, but this is already supported (dual instance mode has the same requirement). However, to take full advantage of single dispatch mode to reduce register pressure we would also need the ability to store two separate vec4 output values into vec8 registers, which would approximately double our capacity to store temporary values, but currently the vec4 visitor and generator classes do not support this, so at the moment register pressure in single and dual instance modes is the same. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* ilo: rename ILO_DEBUG=3dChia-I Wu2014-09-195-6/+6
| | | | | | It has been a bad name since we added the builder. Rename it to ILO_DEBUG=batch to match i965, and call ilo_builder_decode() from ilo_cp_submit_internal().
* ilo: rename ilo_cp_flush()Chia-I Wu2014-09-1911-52/+52
| | | | | | "Flush" is used for too many things already: pipe resource flush, pipe context flush, pipe transfer region flush, and hardware pipeline flush. Rename it to ilo_cp_submit(). As such, ILO_DEBUG=flush is renamed to ILO_DEBUG=submit.
* ilo: remove ilo_cp_empty()Chia-I Wu2014-09-193-22/+12
| | | | Call ilo_builder_batch_used() directly.
* ilo: simplify ilo_cp_set_owner()Chia-I Wu2014-09-195-129/+121
| | | | | | The simplification allows us to get rid of ilo_cp_set_ring() and ilo_cp_implicit_flush(). The 3D query code is refactored for the simplification.
* mesa: Delete VAO _MaxElement code and index buffer bounds checking.Kenneth Graunke2014-09-1915-206/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fredrik's implementation of ARB_vertex_attrib_binding introduced new gl_vertex_attrib_array and gl_vertex_buffer_binding structures, and converted Mesa's older gl_client_array to be derived state. Ultimately, we'd like to drop gl_client_array and use those structures directly. One hitch is that gl_client_array::_MaxElement doesn't correspond to either structure (unlike every other field), so we'd have to figure out where to store it. The _MaxElement computation uses values from both structures, so it doesn't really belong in either place. We could put it in the VAO, but we'd have to pass it around everywhere. It turns out that it's only used when ctx->Const.CheckArrayBounds is set, which is only set by the (rarely used) classic swrast driver. It appears that drivers/x11 used to set it as well, which was intended to avoid segmentation faults on out-of-bounds memory access in the X server (probably for indirect GLX clients). However, ajax deleted that code in 2010 (commit 1ccef926be46dce3b6b5c76e812e2fae4e205ce7). The bounds checking apparently doesn't actually work, either. Non-VBO attributes arbitrarily set _MaxElement to 2 * 1000 * 1000 * 1000. vbo_save_draw and vbo_exec_draw remark /* ??? */ when setting it, and the i965 code contains a comment noting that _MaxElement is often bogus. Given that the code is complex, rarely used, and dubiously functional, it doesn't seem worth maintaining going forward. This patch drops it. This will probably mean the classic swrast driver may begin crashing on out of bounds vertex buffer access in some cases, but I believe that is allowed by OpenGL (and probably happened for non-VBO accesses anyway). There do not appear to be any Piglit regressions, either. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* vc4: Add support for stencil operations.Eric Anholt2014-09-188-2/+118
| | | | | | | While depth test state is passed through the fragment shader as sideband, data, the stencil test state has to be set by the fragment shader itself. Many tests are still failing, but this gets most of hiz/ passing.
* vc4: Actually implement VC4_DEBUG=cl.Eric Anholt2014-09-184-0/+141
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* draw: (trivial) remove duplicated linesRoland Scheidegger2014-09-181-12/+0
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* mesa: fix prog_optimize.c assertions triggered by SWZ opcodeBrian Paul2014-09-181-5/+4
| | | | | | | | | | | | | The SWZ instruction can have swizzle terms >4 (SWIZZLE_ZERO, SWIZZLE_ONE). These swizzle terms caused a few assertions to fail. This started happening after the commit "mesa: Actually use the Mesa IR optimizer for ARB programs." when replaying some apitrace files. A new piglit test (tests/asmparsertest/shaders/ARBfp1.0/swz-08.txt) exercises this. Cc: "10.3" <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* vc4: Allow copy propagation of uniforms.Eric Anholt2014-09-171-1/+15
| | | | | Fixes 12 piglit tests (and 8 more crash -> fail) from reducing register pressure.
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