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* gallivm: disable f16c when not using AVXRoland Scheidegger2015-10-261-0/+3
| | | | | | | | | | | | | | | | | f16c intrinsic can only be emitted when AVX is used. So when we disable AVX due to forcing 128bit vectors we must not use this intrinsic (depending on llvm version, this worked previously because llvm used AVX even when we didn't tell it to, however I've seen this fail with llvm 3.3 since 718249843b915decf8fccec92e466ac1a6219934 which seems to have the side effect of disabling avx in llvm albeit it only touches sse flags really, but with ea421e919ae6e72e1319fb205c42a6fb53ca2f82 it's now really disabled). Albeit being able to use AVX with 128bit vectors also would have its uses, the code as is really was meant to emulate jit code creation for less capable cpus. v2: add some (ifdefed out) missing de-featuring options for simulating less capable cpus. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/va: pass picture desc to begin and decodeJulien Isorce2015-10-261-2/+2
| | | | | | | | | | At least vl_mpeg12_decoder uses the picture desc in begin_frame and decode_bitstream. https://bugs.freedesktop.org/show_bug.cgi?id=92634 Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* mesa: add additional checks for uniform location queryTapani Pälli2015-10-261-0/+8
| | | | | | | | | | | | | | | | Patch adds additional check to make sure we don't return locations for structures or arrays of structures. From page 79 of the OpenGL 4.2 spec: "A valid name cannot be a structure, an array of structures, or any portion of a single vector or a matrix." v2: use without-array() to simplify code (Timothy) No Piglit or CTS regressions observed. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* docs: add news item and link release notes for 11.0.4Emil Velikov2015-10-252-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 11.0.4Emil Velikov2015-10-251-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit ec14e6f8fd05999b482e0785d8cd286042c9c254)
* docs: add release notes for 11.0.4Emil Velikov2015-10-251-0/+167
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 31bf24703193cc23961923e01548b1acb2760a93)
* i965: Make brw_varying_to_offset take a const pointer to the VUE map.Kenneth Graunke2015-10-241-2/+2
| | | | | | | It doesn't modify it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* vc4: Fix names of the 16-bit unpacksEric Anholt2015-10-243-6/+6
| | | | | They're only f16-to-f32 on a float operation, otherwise they're i16-to-i32.
* vc4: Don't try to register coalesce into the VPM across non-raw MOVs.Eric Anholt2015-10-241-1/+1
| | | | | No known bugs, just something I noticed while updating optimization code for other changes.
* vc4: Take advantage of the 8888 pack function in pack_unorm_4x8.Eric Anholt2015-10-241-0/+14
| | | | | | | | | | One instruction instead of four, and it turns out you do this a lot for the Over operator. total uniforms in shared programs: 32168 -> 32087 (-0.25%) uniforms in affected programs: 318 -> 237 (-25.47%) total instructions in shared programs: 89830 -> 89472 (-0.40%) instructions in affected programs: 6434 -> 6076 (-5.56%)
* vc4: Fix the test for skipping raw MOVs.Eric Anholt2015-10-243-1/+10
| | | | | I don't know what previous test was trying to do, but it dates back to the first add of vc4_qpu_emit.c. No change to shader-db.
* i965: Remove unused devinfo revisionBen Widawsky2015-10-243-5/+13
| | | | | | | | | | | | | | | | I left the function to obtain the revision because it is, and will continue to be useful in the future. I'd rather not have to dig it up every time we need it. Comments left at the implementation to say as much. This was accidentally left here when I moved the early platform support: commit 28ed1e08e8ba98ebd4ff0b56326372f0df9c73ad Author: Ben Widawsky <[email protected]> Date: Fri Aug 7 13:58:37 2015 -0700 i965/skl: Remove early platform support Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* docs/index.html: fix typoFabio Pedretti2015-10-241-1/+1
| | | | | Reviewed-by: Boyan Ding <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* freedreno: remove unnecessary null checksRob Clark2015-10-244-13/+13
| | | | | | | | According to piglit/xonotic/neverball/stc, blend/rasterize/zsa state will always be bound (never null). And the null checks were in- consistent anyways, so remove them. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Implement DCC fast clear.Bas Nieuwenhuizen2015-10-243-14/+100
| | | | | | | | | | | Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. v2 Marek: check dcc_buffer && dirty_level_mask in set_sampler_view Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallivm: fix tex offsets with mirror repeat linearRoland Scheidegger2015-10-241-4/+5
| | | | | | | | Can't see why anyone would ever want to use this, but it was clearly broken. This fixes the piglit texwrap offset test using this combination. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: fix sampling with texture offsets in SoA pathRoland Scheidegger2015-10-241-3/+8
| | | | | | | | | | | | | When using nearest filtering and clamp / clamp to edge wrapping results could be wrong for negative offsets. Fix this by adding the offset before doing the conversion to int coords (could also use floor instead of trunc int conversion but probably more complex on "typical" cpu). This fixes the piglit texwrap offset failures with this filter/wrap combo (which only leaves the linear/mirror repeat combination broken). Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: fix using non-zero layer in non-array view from array resourceRoland Scheidegger2015-10-242-9/+31
| | | | | | | | | | | | For vertex/geometry shader sampling, this is the same as for llvmpipe - just use the original resource target. For fragment shader sampling though (which does not use first-layer based mip offsets) adjust the sampling code to use first_layer in the non-array cases. While here also fix up some code which looked wrong wrt buffer texel fetch (no piglit change). Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix using non-zero layer in non-array view from array resourceRoland Scheidegger2015-10-242-8/+8
| | | | | | | | | | | Just need to use resource target not view target when calculating first-layer based mip offsets. (This is a gl specific problem since d3d10 does not distinguish between non-array and array resources neither at the resource nor view level, only at the shader level.) Fixes new piglit arb_texture_view sampling-2d-array-as-2d-layer test. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: add Stoney to si_init_gs_info()Alex Deucher2015-10-231-0/+1
| | | | | | | | This patch was originally written before stoney support was merged. Add stoney. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: Enable DCC.Bas Nieuwenhuizen2015-10-246-6/+50
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Add FLUSH_AND_INV_CB_DATA_TS for DCC.Bas Nieuwenhuizen2015-10-241-0/+11
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Disable operations that do not work with DCC.Bas Nieuwenhuizen2015-10-244-3/+11
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: Allocate buffers for DCC.Bas Nieuwenhuizen2015-10-245-5/+92
| | | | | | | | | | | As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. DCC is disabled for textures that can be shared as sharing the DCC buffers has not been implemented yet. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: only apply the SNORM blit workaround to *8_SNORMMarek Olšák2015-10-241-1/+1
| | | | | | | Like the comment says. This fixes DCC, which doesn't like blitting RG16 as RGBA8. Reviewed-by: Michel Dänzer <[email protected]>
* util/format: add helper util_format_is_snorm8Marek Olšák2015-10-242-0/+22
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add another requirement for PARTIAL_ES_WAVEMarek Olšák2015-10-244-2/+35
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: merge two ifs setting WD_SWITCH_ON_EOPMarek Olšák2015-10-241-5/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: make PARTIAL_ES_WAVE globally dependent on SWITCH_ON_EOIMarek Olšák2015-10-241-5/+6
| | | | | | This catches the other cases that enable SWITCH_ON_EOI. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add one more SWITCH_ON_EOI requirement for Hawaii and VIMarek Olšák2015-10-241-1/+10
| | | | | | The VI condition depends on geometry shaders and MAX_PRIMGRP_IN_WAVE. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only apply the instancing bug workaround to BonaireMarek Olšák2015-10-241-5/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add SWITCH_ON_EOI requirement for 4 SE partsMarek Olšák2015-10-241-0/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unnecessary PARTIAL_VS_WAVE setting for streamoutMarek Olšák2015-10-241-4/+0
| | | | | | hardware does this automatically Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: allow unbinding vertex shadersMarek Olšák2015-10-241-2/+2
| | | | | | Draw calls without a vertex shader are skipped. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: allow unbinding pixel shaders and remove the dummy shaderMarek Olšák2015-10-243-22/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add draw_vbo check for a NULL pixel shaderMarek Olšák2015-10-243-1/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add checks for a NULL pixel shaderMarek Olšák2015-10-242-32/+42
| | | | | | This will allow removing the dummy PS. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/util: add a test for NULL fragment shadersMarek Olšák2015-10-241-0/+38
| | | | | | Just to validate that radeonsi doesn't crash. Reviewed-by: Michel Dänzer <[email protected]>
* st/mesa: don't load state parameters if there are noneMarek Olšák2015-10-241-1/+2
| | | | | | | | | Out of 7063 shaders from my shader-db: - 6564 (93%) shaders don't have any state parameters. - 347 (5%) shaders have 1 state parameter for WPOS lowering. - The remaining 2% have more state parameters, usually matrices. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: add Stoney pci idsSamuel Li2015-10-231-0/+2
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeonsi: add support for Stoney asics (v3)Samuel Li2015-10-235-3/+19
| | | | | | | | | | | v2 (agd): rebase on mesa master, split pci ids to separate commit v3 (agd): use carrizo for llvm processor name for llvm 3.7 and older Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* nvc0: respect edgeflag attribute widthIlia Mirkin2015-10-231-7/+33
| | | | | | | | | | | | The edgeflag comes in as ubyte with glEdgeFlagPointer but as float with plain immediate glEdgeFlag. Avoid reading bytes that weren't meant for the edgeflag in the pointer case. Fixes intermittent failures with gl-2.0-edgeflag piglit (and valgrind complaints about reading uninitialized memory). Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gallivm: Explicitly disable unsupported CPU features.Jose Fonseca2015-10-231-38/+34
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92214 CC: "10.6 11.0" <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* vc4: Convert blending to being done in 4x8 unorm normally.Eric Anholt2015-10-235-51/+276
| | | | | | | | | | | | | We can't do this all the time, because you want blending to be done in linear space, and sRGB would lose too much precision being done in 4x8. The win on instructions is pretty huge when you can, though. total uniforms in shared programs: 32065 -> 32168 (0.32%) uniforms in affected programs: 327 -> 430 (31.50%) total instructions in shared programs: 92644 -> 89830 (-3.04%) instructions in affected programs: 15580 -> 12766 (-18.06%) Improves openarena performance at 1920x1080 from 10.7fps to 11.2fps.
* vc4: Add QIR/QPU support for the 8-bit vector instructions.Eric Anholt2015-10-234-0/+45
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* vc4: Don't try to CSE non-SSA instructions.Eric Anholt2015-10-231-0/+1
| | | | | | | This can happen when we're doing destination packing -- we don't know what's in the rest of the register. Signed-off-by: Eric Anholt <[email protected]>
* nir: Add opcodes for saturated vector math.Eric Anholt2015-10-232-0/+51
| | | | | | | | | This corresponds to instructions used on vc4 for its blending inside of shaders. I've seen these opcodes on other architectures before, but I think it's the first time these are needed in Mesa. v2: Rename to 'u' instead of 'i', since they're all 'u'norm (from review by jekstrand)
* vc4: Add dumping of VC4_PACKET_GL_INDEXED_PRIMITIVE.Eric Anholt2015-10-231-1/+22
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* vc4: Add a workaround for HW-2116 (state counter wrap fails).Eric Anholt2015-10-233-6/+40
| | | | | | I haven't proven that this happens (I've got other GPU hangs in the way), but the closed driver also does this and it's documented as an errata.
* vc4: Fix missing \n in a perf_debug().Eric Anholt2015-10-231-1/+1
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