aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* i965: use uncompressed instruction to ensure onlyXiang, Haihao2007-11-301-0/+1
| | | | | Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
* [i915] Make INTEL_DEBUG=bufmgr actually do things for bufmgr_fake.Eric Anholt2007-11-293-6/+17
|
* New ctx->Driver.Map/UnmapTexture() functions for accessing textures from ↵Brian2007-11-294-1/+56
| | | | t_vb_program.c
* cleanups, commentsBrian2007-11-291-27/+28
|
* Move _mesa_load_tracked_matrices() from TNL module to prog_statevars.cBrian2007-11-294-102/+101
|
* r200: Fix texture format regression on big endian systems.Michel Dänzer2007-11-281-3/+6
| | | | | | | See https://bugs.freedesktop.org/show_bug.cgi?id=13324 . Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets called for MESA_FORMAT_RGB888.
* i965: update RefCount when using Vertex/Fragment program.Xiang, Haihao2007-11-281-0/+2
| | | | It makes quake4-demo works well on 965.
* remove drawable from hash table when window is deleted (see bug 13091)WuNian2007-11-271-0/+1
|
* use DEFAULT_SOFTWARE_DEPTH_BITSDelle2007-11-271-9/+11
|
* minor additions to avoid FAQsBrian2007-11-271-0/+6
|
* document GLSL float f/F suffix bugBrian2007-11-271-0/+1
|
* set fp->UsesKill when emitting OPCODE_KILBrian2007-11-271-2/+8
|
* add a few more logicop modes, simplify codeBrian2007-11-271-52/+45
|
* improve 24-bit Z to 32-bit Z conversionBrian2007-11-271-2/+3
|
* i965: The jump instruction count is addedXiang, Haihao2007-11-271-1/+1
| | | | | | to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code
* i915: Catch cases where not all state is emitted for a new batchbuffer.Keith Whitwell2007-11-266-1/+56
| | | | This could lead to incorrect rendering or even lockups.
* i915: Some additional blit fixes and assertions.Michel Dänzer2007-11-261-8/+24
|
* libGL: Make sure a valid value is returned for GLX_BIND_TO_MIPMAP_TEXTURE_EXT.Michel Dänzer2007-11-251-1/+2
| | | | | | | | | If the server didn't send a value, assume it's not supported. A more generic solution might be better for this kind of problem, but an attempt for this failed (see https://bugs.freedesktop.org/show_bug.cgi?id=9264) and this allows compiz to work with drivers that support GL_EXT_framebuffer_object.
* intel: Fix relative symlinks.Michel Dänzer2007-11-252-2/+2
|
* better test of point attenuationBrian2007-11-231-23/+33
|
* #define GL_GLEXT_PROTOTYPES to silence warningBrian2007-11-231-0/+1
|
* Consolidate texture fetch code and use partial derivatives when possible.Brian2007-11-233-75/+79
|
* Fix parsing of gl_FrontLightModelProduct.sceneColor, don't segfault on ↵Brian2007-11-232-5/+15
| | | | variable array indexes.
* need to check border width in sample_linear_2d() - fixes failed assertion in ↵Brian2007-11-231-1/+2
| | | | texwrap.c test
* Consolidate point size computation, clamping in get_size().Brian2007-11-221-36/+35
| | | | | Also, apply user-defined clamp limits to point size even when not using attentuation or program-computed size.
* Print point/line size range limitsBrian2007-11-221-1/+11
|
* fix z buffer read/write issue with rv100-like chips and old ddxRoland Scheidegger2007-11-221-1/+5
|
* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-208-187/+8
| | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
* [965] Remove dead exec vfmt code which was replaced by generic vbo code.Eric Anholt2007-11-201-530/+0
|
* clamp lambda to Min/MaxLodBrian2007-11-201-3/+6
|
* [965] Add INTEL_DEBUG=fall debugging output.Eric Anholt2007-11-191-5/+17
|
* [965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt2007-11-1912-16/+31
|
* fix some texture format assertions, etcBrian2007-11-191-23/+11
|
* fix out-of-bounds array index (ix=-1)Brian2007-11-191-2/+3
|
* [intel] Add 965 support to shared intel_blit.cEric Anholt2007-11-1612-75/+119
| | | | | This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
* [i915] Pass static region names in so debugging says more than "static region".Eric Anholt2007-11-163-12/+17
|
* [intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt2007-11-164-59/+87
|
* [intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt2007-11-161-0/+0
|
* [965] Add batchbuffer decode for several more packets.Eric Anholt2007-11-161-3/+127
|
* [intel] Fix typos in intel_chipset.h macros.Eric Anholt2007-11-161-6/+6
|
* [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt2007-11-163-0/+8
|
* [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.Eric Anholt2007-11-161-4/+4
|
* [intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt2007-11-161-2/+11
|
* [intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt2007-11-161-35/+91
| | | | | This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
* [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt2007-11-161-0/+4
| | | | They shouldn't be created, and this often helps catch stupid issues.
* [intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt2007-11-162-73/+163
| | | | | This is required for 965 support, which has relocations in other places than just the batchbuffer.
* [i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt2007-11-162-85/+72
| | | | | | | | | The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
* added z/s keys to reset/step rotationBrian2007-11-161-2/+12
|
* Only emit texcoords for enabled units. Enable/disable units with 0..7 keys.Brian2007-11-161-58/+65
| | | | Also, asst. clean-ups.
* fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger2007-11-151-2/+1
| | | | | | | | this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 01:12:35 +0000