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* nir: Add a helper for fetching the SSA def from an instructionJason Ekstrand2019-07-162-0/+49
| | | | Reviewed-by: Eric Anholt <[email protected]>
* pandecode: Add more addresses to traceTomeu Vizoso2019-07-161-5/+5
| | | | | | | When debugging, we're given the fault_pointer unresolved, so it is helpful to have more context in the decode. Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost: Use 64-bit descriptors globallyTomeu Vizoso2019-07-165-67/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Midgard supports two modes of operation, 32-bit mode and 64-bit mode. The GPU is natively 64-bit, but job descriptors can be submitted in 32-bit mode. Among other changes, 32-bit mode shortens pointer sizes to use 32-bit pointers rather than the full 64-bit range. The blob decides which mode to use based on the CPU bitness, so an armhf system uses 32-bit descriptors and an aarch64 system uses 64-bit descriptors. For a while, we mimicked this, bu inevitably this caused the 32-bit support to lag behind as our reference platform is 64-bit. To combat the code staleness, we traced an older GPU paired with a 64-bit CPU (the Midgard T720 on-board the sunxi H64). From there, we could tell which fields were really about hardware and which fields were simply reflections of the descriptor bitness. From there, we decided to remove support for 32-bit descriptors entirely, using 64-bit descriptors unconditionally. There is minimal performance penalty for this in practice, and it allows us to unify these disparate code paths. This fixes: - T860 + armhf - T820 + armhf - T760 + aarch64 And will help bringup of 1st/2nd generation Midgard regardless of CPU. [Work done by Tomeu. Commit message written by Alyssa.] v2: Add comments preserving information about the old behaviour for future reference. Fix a compiler warning. (Alyssa) Signed-off-by: Alyssa Rosenzweig <[email protected]>
* anv: Account for dynamic stencil write disables in the PMA fixJason Ekstrand2019-07-161-0/+2
| | | | | | | | | | | In 6ce8592836b8 we started looking at the dynamic stencil state and disabling stencil writes when the stencil mask is zero. Unfortunately, we never updated the PMA fix code accordingly so 3DSTATE_WM_DEPTH_STENCIL and the PMA fix were getting out-of-sync causing hangs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109203 Fixes: 6ce8592836 "anv: Disable stencil writes when both write..." Reviewed-by: Lionel Landwerlin <[email protected]>
* panfrost: Implement opportunistic AFBCAlyssa Rosenzweig2019-07-165-1/+100
| | | | | | | | | | | | | | | | Rather than hardcoding a BO layout at creation-time, we implement the ability to hint layouts at various points in a BO's lifetime, potentially reallocating and switching layouts if it's heuristically deemed useful to do so. In this patch, we add a simple hinting implementation, opportunistically compressing FBOs. Support is hidden behind PAN_MESA_DEBUG=afbc as the implementation is incomplete (software access to AFBC is unimplemented at the moment) and therefore would regress significantly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Zero out framebuffer_strideAlyssa Rosenzweig2019-07-161-2/+3
| | | | | | We don't know what this is, so let's not pretend we do. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: AFBC buffers must be cache-line alignedAlyssa Rosenzweig2019-07-161-0/+5
| | | | | | Fixes a DATA_INVALID_FAULT when AFBC is paried with mipmapping. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add Z/S and MRT BOs to the jobAlyssa Rosenzweig2019-07-162-10/+12
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Set usage2 during draw, not CSOAlyssa Rosenzweig2019-07-162-24/+37
| | | | | | It can change from a layout switch. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* meta: memory leak of CopyPixels usageSergii Romantsov2019-07-161-0/+14
| | | | | | | | | Meta of CopyPixel generates a buffer object but does not free it on cleanup. Fixes: 37d11b13ce1d (meta: Don't pollute the buffer object namespace in _mesa_meta_setup_vertex_objects) Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radv: add radv_emit_streamout_{begin,end} helpersSamuel Pitoiset2019-07-161-8/+35
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: pass output values to radv_emit_stream_output()Samuel Pitoiset2019-07-161-13/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: allow to select DST_SEL with RELEASE_MEMSamuel Pitoiset2019-07-164-3/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: allow to emit PS_DONE/CS_DONE with RELEASE_MEMSamuel Pitoiset2019-07-161-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: restore an assertion in handle_vs_outputs()Samuel Pitoiset2019-07-161-1/+1
| | | | | | | | The NGG GS epilogue no longers call that function so the assertion is just useless now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx10: emit ES outputs of TES when it's not NGGSamuel Pitoiset2019-07-161-3/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: update LATE_ALLOC_VS.LIMITSamuel Pitoiset2019-07-161-18/+42
| | | | | | | Mirror RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx10: support pixel shaders without exportsSamuel Pitoiset2019-07-161-1/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: fix gathering clip/cull distance masks for GSSamuel Pitoiset2019-07-161-0/+5
| | | | | | | | | | For NGG, the driver relies on the VS outinfo struct. This fixes dEQP-VK.clipping.user_defined.clip_*_vert_tess_geom_* Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* Revert "radv/gfx10: don't set array pitch field on images"Samuel Pitoiset2019-07-161-1/+1
| | | | | | It introduces too many regressions. This reverts commit 6d50dcd80fc120fdabcd57ef576f3e45ea2724e4.
* v3d: flag dirty state when binding new sampler statesIago Toral Quiroga2019-07-161-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We emit code to saturate texture coordinates when using clamp wrapping mode so if we don't flag the dirty state here we don't get to recompile the shaders when the wrapping mode changes. v2: - Do the same when setting sampler views (Eric) - Use a switch statement instead of an if ladder. - Swap the shader stage assertion with an unreachable. Fixes: spec/!opengl 1.1/texwrap 1d bordercolor/gl_rgba8, border color only spec/!opengl 1.1/texwrap 1d proj bordercolor/gl_rgba8, projected, border color only spec/!opengl 1.1/texwrap 2d bordercolor/gl_rgba8, border color only spec/!opengl 1.1/texwrap 2d proj bordercolor/gl_rgba8, projected, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha12, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha16, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_alpha8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_intensity8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance4_alpha4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance6_alpha2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_luminance8_alpha8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_r3_g3_b2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb10, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb10_a2, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb5, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb5_a1, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgb8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgba4, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor-swizzled/gl_rgba8, swizzled, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha12, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha16, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_alpha8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_intensity8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance4_alpha4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance6_alpha2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_luminance8_alpha8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_r3_g3_b2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb10, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb10_a2, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb5, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb5_a1, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgb8, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgba4, border color only spec/!opengl 1.1/texwrap formats bordercolor/gl_rgba8, border color only spec/!opengl 1.2/texwrap 3d bordercolor/gl_rgba8, border color only spec/!opengl 1.2/texwrap 3d proj bordercolor/gl_rgba8, projected, border color only spec/arb_es2_compatibility/texwrap formats bordercolor-swizzled/gl_rgb565, swizzled, border color only spec/arb_es2_compatibility/texwrap formats bordercolor/gl_rgb565, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_alpha, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_luminance_alpha, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgb, swizzled, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_alpha, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_luminance_alpha, border color only spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgb, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_alpha16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_intensity16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_luminance16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_luminance_alpha16f_arb, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_rgb16f, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor-swizzled/gl_rgba16f, swizzled, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_alpha16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_intensity16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_luminance16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_luminance_alpha16f_arb, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_rgb16f, border color only spec/arb_texture_float/texwrap formats bordercolor/gl_rgba16f, border color only spec/arb_texture_rectangle/texwrap rect bordercolor/gl_rgba8, border color only spec/arb_texture_rectangle/texwrap rect proj bordercolor/gl_rgba8, projected, border color only spec/arb_texture_rg/texwrap formats bordercolor-swizzled/gl_r8, swizzled, border color only spec/arb_texture_rg/texwrap formats bordercolor-swizzled/gl_rg8, swizzled, border color only spec/arb_texture_rg/texwrap formats bordercolor/gl_r8, border color only spec/arb_texture_rg/texwrap formats bordercolor/gl_rg8, border color only spec/arb_texture_rg/texwrap formats-float bordercolor-swizzled/gl_r16f, swizzled, border color only spec/arb_texture_rg/texwrap formats-float bordercolor-swizzled/gl_rg16f, swizzled, border color only spec/arb_texture_rg/texwrap formats-float bordercolor/gl_r16f, border color only spec/arb_texture_rg/texwrap formats-float bordercolor/gl_rg16f, border color only spec/ext_packed_float/texwrap formats bordercolor-swizzled/gl_r11f_g11f_b10f, swizzled, border color only spec/ext_packed_float/texwrap formats bordercolor/gl_r11f_g11f_b10f, border color only spec/ext_texture_shared_exponent/texwrap formats bordercolor-swizzled/gl_rgb9_e5, swizzled, border color only spec/ext_texture_shared_exponent/texwrap formats bordercolor/gl_rgb9_e5, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_alpha8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_intensity8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_luminance8_alpha8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_luminance8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_r8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rg8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rgb8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor-swizzled/gl_rgba8_snorm, swizzled, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_alpha8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_intensity8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_luminance8_alpha8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_luminance8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_r8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rg8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rgb8_snorm, border color only spec/ext_texture_snorm/texwrap formats bordercolor/gl_rgba8_snorm, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_sluminance8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_sluminance8_alpha8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_srgb8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor-swizzled/gl_srgb8_alpha8, swizzled, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_sluminance8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_sluminance8_alpha8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_srgb8, border color only spec/ext_texture_srgb/texwrap formats bordercolor/gl_srgb8_alpha8, border color only Reviewed-by: Eric Anholt <[email protected]>
* radv/gfx10: add missing conversions for 16-bit exportsSamuel Pitoiset2019-07-161-0/+9
| | | | | | | | | | This fixes dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_* Found with RADV_DEBUG=checkir Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused code in radv_export_param()Samuel Pitoiset2019-07-161-15/+1
| | | | | | | It was hack for geometry shaders. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: don't set array pitch field on imagesDave Airlie2019-07-161-1/+1
| | | | | | | | | | Setting this seems to be broken, amdvlk only sets it for quilted textures which I'm not sure what those are. Fixes dEQP-VK.glsl.texture_functions.query.texturesize*3d* Fixes: bf11f1c3a47 ("radv/gfx10: add gfx10_make_texture_descriptor") Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* lima/ppir: Fix assert condition in ppir_codegen_encode_branch.Vinson Lee2019-07-151-1/+1
| | | | | | | Fixes: af0de6b91c0b ("lima/ppir: implement discard and discard_if") Reported-by: Coverity Scan Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* docs: Tell people how to easily generate the Fixes lines.Eric Anholt2019-07-151-0/+1
| | | | | | | | | v2: Include '-s' to suppress the diff. v3: use the git config command (Ken), use &lt; (Eric) Reviewed-by: Matt Turner <[email protected]> (v1) Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: Ignore ArrayStride for storage classes that should not use itCaio Marcelo de Oliveira Filho2019-07-151-4/+18
| | | | | | | | The stride was already overriden when using lower_workgroup_access_to_offsets, so elaborate a bit the commentary there. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Fix stride calculation when lowering Workgroup to offsetsCaio Marcelo de Oliveira Filho2019-07-151-1/+1
| | | | | | | | | | | | Use alignment to calculate the stride associated with the pointer types. That stride is used when the pointers are casted to arrays. Note that size alone is not sufficient, e.g. struct { vec2 a; vec1 b; } will have element an element size of 12 bytes, but the stride needs to be 16 bytes to respect the 8 byte alignment. Fixes: 050eb6389a8 "spirv: Ignore ArrayStride in OpPtrAccessChain for Workgroup" Reviewed-by: Jason Ekstrand <[email protected]>
* panfrost/ci: Blacklist flush finish testsAlyssa Rosenzweig2019-07-151-0/+1
| | | | | | | | We don't implement batch splitting quite yet which is necessary for the ludicrous number of draw calls these tests invoke. Blacklist them for now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't leak oversized transient allocationsAlyssa Rosenzweig2019-07-151-0/+4
| | | | | | | When we allocate them, we allocate with two references accidentally, causing them to leak uncontrollably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement panfrost_bo_cache_evict_allAlyssa Rosenzweig2019-07-151-1/+9
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement panfrost_bo_cache_getAlyssa Rosenzweig2019-07-151-1/+16
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement panfrost_bo_cache_putAlyssa Rosenzweig2019-07-151-2/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add pan_bucket helperAlyssa Rosenzweig2019-07-151-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement pan_bucket_index helperAlyssa Rosenzweig2019-07-151-0/+25
| | | | | | We'll use this whenever we need to lookup a bucket. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add BO cache data structureAlyssa Rosenzweig2019-07-153-0/+24
| | | | | | Linked list of panfrost_bo* nested inside an array of buckets. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Describe BO cache architectureAlyssa Rosenzweig2019-07-151-0/+20
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Stub out panfrost_bo_cache_evictAlyssa Rosenzweig2019-07-153-0/+17
| | | | | | | This destructor will be used to legitimately free the BOs, now that a BO free with cacheable=0 is only a "fake" free. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Stub out panfrost_bo_cache_putAlyssa Rosenzweig2019-07-154-3/+34
| | | | | | ..so we can intercept the BO free. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Stub out panfrost_bo_cache_getAlyssa Rosenzweig2019-07-154-10/+66
| | | | | | | We will use this function to fetch cached BOs instead of freshly allocating them. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't leak the blend CSO hash tableAlyssa Rosenzweig2019-07-151-3/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Cleanup after scoreboardingAlyssa Rosenzweig2019-07-151-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allocate UBOs on the stack, not the heapAlyssa Rosenzweig2019-07-153-2/+5
| | | | | | | Saves a call to calloc (the maximum size is small and known at compile-time) and fixes a leak. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* nir,intel: Add support for lowering 64-bit nir_opt_extract_*Jason Ekstrand2019-07-153-1/+41
| | | | | | | | | We need this when doing full software 64-bit emulation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110309 Fixes: cbad201c2b3 "nir/algebraic: Add missing 64-bit extract_[iu]8..." Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/opt_if: Clean up single-src phis in opt_if_loop_terminatorJason Ekstrand2019-07-153-0/+16
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111071 Fixes: 2a74296f24ba "nir: add opt_if_loop_terminator()" Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: verify buffer_offset value before using itPierre-Eric Pelloux-Prayer2019-07-151-0/+7
| | | | | | | | | | | | | | This buffer_ofset can come directly from the application (e.g: when using glVertexAttribPointer) and can contain an invalid value. st_atom_array already makes sure that if it's not negative so all that's left is to verify that it's smaller that the buffer size. Bugs related to this issue: Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105251#c52 Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=109693 Signed-off-by: Marek Olšák <[email protected]>
* st/mesa: verify that vertex buffer offset isn't negativePierre-Eric Pelloux-Prayer2019-07-153-0/+15
| | | | | | | | | | | | | | | | | | | | | | For drivers supporting PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET the buffer_offset value will be interpreted as an signed int. An example of application code causing a negative offset: float b[] = { ... }; // 3 float for pos, 3 for color glBufferData(GL_ARRAY_BUFFER, ..., b, ...); glVertexAttribPointer(0, 3, GL_FLOAT, GL_FALSE, 6 * sizeof(float), 0); glVertexAttribPointer(1, 3, GL_FLOAT, GL_FALSE, 6 * sizeof(float), &b[3]); ^ should be 3 * sizeof(float) The offset is a ptr so when interpreted as a signed int it can be negative. This commit adds a verification that (int) buffer_offset is not negative - this would indicate an application bug. Since it's too late to emit a GL_INVALID_VALUE error, we replace the negative offset by 0 and emit a debug message. Signed-off-by: Marek Olšák <[email protected]>
* st/mesa: don't invalidate a buffer range that is mappedMarek Olšák2019-07-151-6/+21
| | | | | This is needed to fix an issue with OpenGL when a buffer is mapped and BufferSubData is called. In this case, we can't invalidate the buffer range.
* gallium: use MAP_DIRECTLY to mean supression of DISCARD in buffer_subdataMarek Olšák2019-07-156-21/+34
| | | | | This is needed to fix an issue with OpenGL when a buffer is mapped and BufferSubData is called. In this case, we can't invalidate the buffer range.
* iris: Better handle decoder base addressesKenneth Graunke2019-07-151-0/+3
| | | | | | | | | | | | | | It can be useful to call the decoder on a single batch. But, that batch may not contain STATE_BASE_ADDRESS, at which point the decoder will have no idea how to find any buffers. We can initialize the two static bases at the beginning of time, so it has them even if it never sees SBA. Surface base address changes dynamically, possibly in the middle of a batch. So we update it at the start of each batch, making it always start at the value we inherited from the previous one. SBA commands inside the batch can update it to a proper value. Reviewed-by: Jordan Justen <[email protected]>
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