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* aco: Fix workgroup size calculation.Timur Kristóf2020-03-305-35/+39
* aco: Extract setup_tcs_info to a separate function.Timur Kristóf2020-03-301-12/+19
* aco: Zero-fill undefined elements in create_vec_from_array.Timur Kristóf2020-03-301-7/+15
* aco: Change isel inputs/outputs to a flat array.Timur Kristóf2020-03-302-20/+25
* aco: Treat outputs of the previous stage as inputs of the next stage.Timur Kristóf2020-03-302-21/+28
* nir: Collect if shader uses cross-invocation or indirect I/O.Timur Kristóf2020-03-302-13/+110
* aco: Use more optimal sequence at the beginning of merged shaders.Timur Kristóf2020-03-301-3/+17
* aco: Skip 2nd read of merged wave info when TCS in/out vertices are equal.Timur Kristóf2020-03-302-6/+18
* aco: Allow combining LDS loads when loading tess factors.Timur Kristóf2020-03-301-13/+13
* aco: Allow combining TCS output VMEM stores.Timur Kristóf2020-03-301-1/+1
* aco: Fix handling of tess factors.Timur Kristóf2020-03-302-22/+13
* aco: Extract tcs_driver_location_matches_api_mask to separate function.Timur Kristóf2020-03-301-21/+30
* aco: Create null exports in instruction selection instead of assembler.Timur Kristóf2020-03-303-36/+72
* nir: Fix breakage of foreach_list_typed_safe assumptions in loop unrollingDanylo Piliaiev2020-03-301-12/+70
* radeon: switch to 3-spaces stylePierre-Eric Pelloux-Prayer2020-03-3021-9286/+8970
* radeonsi: switch to 3-spaces stylePierre-Eric Pelloux-Prayer2020-03-3052-46736/+42975
* radeon: fix includesPierre-Eric Pelloux-Prayer2020-03-304-0/+9
* ddebug: add missing forward declarationPierre-Eric Pelloux-Prayer2020-03-301-0/+1
* meson: Add VS 4624 warning exclusion to remove piles of LLVM warningsDaniel Stone2020-03-301-1/+3
* meson: disable some more warnings on msvcErik Faye-Lund2020-03-301-1/+3
* CI: Avoid htz4 runner for VS2019Daniel Stone2020-03-301-0/+1
* intel: drop unused include directoriesEric Engestrom2020-03-2810-31/+31
* vulkan: drop unused include directoriesEric Engestrom2020-03-283-3/+3
* meson: inline `inc_common`Eric Engestrom2020-03-2898-158/+199
* meson: use existing variables in inc_commonEric Engestrom2020-03-281-2/+1
* mesa: Change _mesa_exec_malloc argument type.Vinson Lee2020-03-282-3/+3
* gitlab-ci: Update to current templatesMichel Dänzer2020-03-281-4/+4
* Revert "gitlab-ci: Disable jobs for Collabora's LAVA lab"Tomeu Vizoso2020-03-281-4/+4
* radeonsi/gfx10: fix descriptors and compute registers for compute-based cullingMarek Olšák2020-03-281-14/+39
* radeonsi/gfx10: fix the wave size for compute-based cullingMarek Olšák2020-03-285-6/+19
* radeonsi/gfx10: user correct ACQUIRE_MEM packet for compute-based cullingMarek Olšák2020-03-281-8/+23
* radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based cullingMarek Olšák2020-03-281-0/+3
* radeonsi/gfx10: don't use NGG culling if compute-based culling is usedMarek Olšák2020-03-281-0/+1
* radeonsi: add num_vbos_in_user_sgprs into the shader cache keyMarek Olšák2020-03-281-0/+3
* radeonsi: always create wait_mem_scratch for compute-based cullingMarek Olšák2020-03-281-1/+2
* radeonsi: set amdgpu-gds-size for mode == 2 of compute-based cullingMarek Olšák2020-03-281-1/+4
* radeonsi: fix incorrect ordered_wave_id initilization for compute-based cullingMarek Olšák2020-03-281-1/+2
* radeonsi: remove obsolete TODO comment related to compute-based cullingMarek Olšák2020-03-281-1/+0
* lima: Implement lima_texture_subdataVasily Khoruzhick2020-03-281-13/+65
* gitlab-ci: disable vs2019 buildRob Clark2020-03-271-1/+1
* freedreno/ir3/ra: re-work a6xx merged register file conflictsRob Clark2020-03-271-18/+10
* freedreno/ir3/ra: split building regs/classes and conflictsRob Clark2020-03-272-22/+73
* freedreno/ir3/ra: pick higher numbered scalars in first passRob Clark2020-03-274-17/+113
* freedreno/ir3/ra: compute register target from liverangesRob Clark2020-03-272-82/+209
* freedreno/ir3/ra: fix array liverangesRob Clark2020-03-271-1/+1
* freedreno/ir3/ra: add def/use iteratorsRob Clark2020-03-272-133/+202
* freedreno/ir3/ra: drop extending output live-rangesRob Clark2020-03-271-7/+0
* freedreno/ir3/ra: add helper to map name to arrayRob Clark2020-03-271-1/+24
* freedreno/ir3/ra: fix target register calculationRob Clark2020-03-271-1/+1
* freedreno/ir3/ra: add helper to map name to instructionRob Clark2020-03-271-23/+36
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