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* iris: Detect DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT kernel supportKenneth Graunke2020-05-012-0/+14
| | | | | | We will use this for implementing deferred flushes in the next commit. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* intel: Move anv_gem_supports_syncobj_wait to common code.Kenneth Graunke2020-05-015-28/+63
| | | | | | | | | This will let me use this in iris. We leave the existing anv function for anv_gem_stubs.c faking, but move the contents to a helper in a new src/intel/common/gen_gem.c file. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Flush any current work in iris_fence_await before adding depsKenneth Graunke2020-05-011-0/+4
| | | | | | | | | Receiving a fence_server_sync (iris_fence_await) means that any future work needs to wait for the fence. But previous work doesn't need to. So flush it now, to avoid delaying it arbitrarily. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Store a seqno for each batch in the fenceChris Wilson2020-05-011-29/+22
| | | | | | | | | | | | In the next patch, we will introduce deferred fences where we will need to flush a fence later. To do this, we need to know which batch requires flushing, so keep a 1:1 mapping between seqno[] and the associated batch. It's also substantially less confusing to have a 1:1 mapping. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Convert fences to using lightweight seqnoChris Wilson2020-05-011-13/+64
| | | | | | | | | | | By using the breadcrumbs we inject into the batch, we can build a lightweight fence - that can be evaluated in userspace without having to check in the kernel. In order to pass the fences between processes, and to wait efficiently, we continue to track the syncobj for each batch and use that as a terminator for the fence, and for passing coarse scheduling decisions to the kernel on execbuf. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Place a seqno at the end of every batchChris Wilson2020-05-016-13/+230
| | | | | | | | | | We can use seqno as a basic for fast userspace fences: where we can check a value directly to test for fence completion without having to query using the kernel. To do so we need to write a breadcrumb from the batch and track those writes as the basis for our lightweight fences. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Destroy transfer slab after batchesKenneth Graunke2020-05-011-2/+2
| | | | | | | | | Batches are going to have an uploader in the next commit, so destroying batches will destroy uploaders, which will unmap transfers, which will return things to the slab allocator. So we need to reorder destroying the slab allocator to the end to avoid crashing. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Give up on not passing ice to iris_init_batchKenneth Graunke2020-05-013-20/+13
| | | | | | | | | We're going to need it to create a uploader in the batch soon. We still avoid storing it, to maintain the charade of separation, and make people think twice about fetching random fields from there and intertwining things even worse. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Rename iris_syncpt to iris_syncobj for clarity.Kenneth Graunke2020-05-015-91/+98
| | | | | | | | This is just a refcounted wrapper around a drm_syncobj. There is enough terminology going on in the area of synchronization (sync objects, sync files, ...) that I'd rather not invent our own. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* anv: Include linux/sync_file.h instead of cut and pasting contentsKenneth Graunke2020-05-011-18/+1
| | | | | | | Linux 4.7 has been out for a long time, this is probably safe to depend on at this point, rather than cut and pasting the contents. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* iris: Include linux/sync_file.h instead of cut and pasting contentsKenneth Graunke2020-05-011-18/+2
| | | | | | | | | | | Lets us drop some cut and pasted kernel header contents. Linux 4.7 came out 4 years before we the first officially supported release of this driver; iris won't run on kernels older than 4.16, and 4.18.11+ is strongly recommended. So I suspect it's safe to assume that a kernel header from 4.7 will exist at build time. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* panfrost: Update dEQP expectation listAlyssa Rosenzweig2020-05-011-2/+0
| | | | | | | These tests were recently fixed. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Enable nir_opt_algebraic_distribute_src_modsAlyssa Rosenzweig2020-05-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Helps cleanup some issues otherwise missed by the new source mod handling. (Noticed a double negative) total instructions in shared programs: 3606 -> 3605 (-0.03%) instructions in affected programs: 41 -> 40 (-2.44%) helped: 1 HURT: 0 total bundles in shared programs: 1883 -> 1883 (0.00%) bundles in affected programs: 0 -> 0 helped: 0 HURT: 0 total quadwords in shared programs: 3296 -> 3324 (0.85%) quadwords in affected programs: 596 -> 624 (4.70%) helped: 0 HURT: 2 total registers in shared programs: 337 -> 336 (-0.30%) registers in affected programs: 6 -> 5 (-16.67%) helped: 1 HURT: 0 Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Drop `opt` in name of midgard_opt_cull_dead_branchAlyssa Rosenzweig2020-05-011-2/+2
| | | | | | | It's necessary for conformance - not an optimization. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Drop forever todoAlyssa Rosenzweig2020-05-011-13/+3
| | | | | | | Not much to be done. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Move constant switch opts to algebraic passAlyssa Rosenzweig2020-05-012-46/+15
| | | | | | | No shader-db changes. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Rename .one to .sat_signedAlyssa Rosenzweig2020-05-012-2/+2
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* pan/mdg: Ingest actual isub opsAlyssa Rosenzweig2020-05-012-1/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4852>
* glthread: Add GLAPIENTRY to _mesa_marshal_MultiDrawArrays.Jose Fonseca2020-05-011-1/+1
| | | | | | Fixes MSVC build. Trivial. Fixes: 2840bc3065b9e991b2c5880a2ee02e2458a758c4
* intel/dev: Bail when INTEL_DEVID_OVERRIDE is not validCaio Marcelo de Oliveira Filho2020-05-011-55/+52
| | | | | | | | | | | | | | | Avoids surprises where you set an OVERRIDE but it gets ignored and the system PCI ID is used. Also fixes the bug that the error of invalid platform name being printed too early, even when the passed platform was a PCI ID (which is also supported). For the case where euid != uid, a warning was added but the behavior wasn't changed: it is still going to fallback to system PCI ID. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4841>
* anv,iris: Fix input vertex max for tcs on gen12D Scott Phillips2020-05-014-3/+10
| | | | | | | | | | | | | gen12 does away with the single patch dispatch mode for tcs, and increases some limits so that 8_patch mode can always work. Make the necessary changes so we don't try to fall back to single patch mode. Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others Fixes: 44754279ace7 ("intel/fs/gen12: Use TCS 8_PATCH mode.") Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4843>
* freedreno/ir3: Set the FS .msaa flag to true during precompiles.Eric Anholt2020-05-011-0/+1
| | | | | | | | If you're going out of your way to do per-sample interpolation, you are almost surely going to be doing so to an MSAA framebuffer. Should reduce recompiles with MSAA enabled. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno: Immediately compile a default variant of shaders.Eric Anholt2020-05-011-44/+39
| | | | | | | | | | Now that we normalize our keys fairly well, build a variant at shader state creation time so that hopefully you don't have to call the compiler at draw time (as is now the case with glmark2 ES and most of the humus GL demos). Fixes: #2782 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Set up outputs for multi-slot varyings.Eric Anholt2020-05-011-20/+25
| | | | | | | | Necessary to avoid compiler assertion failures in: dEQP-GLES31.functional.program_interface_query.program_output.type.interface_blocks.out.named_block_explicit_location.struct.mat3x2 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Stop initializing regid of so->outputs during setup.Eric Anholt2020-05-011-1/+0
| | | | | | It's unused and overwritten by ir3_compile_shader_nir(). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Improve shader key normalization.Eric Anholt2020-05-014-60/+83
| | | | | | | | | | | | | We can remove a bunch of conditional code at key comparison time by computing a bitmask of used key bits at ir3_shader creation time. This also gives us a nice place to put additional key simplification to reduce how many variants we create (like skipping rastflat if we don't read colors in the FS, or skipping vclamp_color if we don't write colors). It does mean walking the whole key to AND it, but the key is just 28 bytes so far so that seems pretty fine. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno: Emit debug messages when doing draw-time recompiles of shaders.Eric Anholt2020-05-012-0/+23
| | | | | | Right now that's "always" unless you have shaderdb set. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Remove unused half precision shader key flag.Eric Anholt2020-05-016-30/+0
| | | | | | | The code using it was removed in 4af86bd0b933 ("freedreno/ir3: remove half-precision output") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno: Fix assertion failures on GS/tess shaders with shader-db enabled.Eric Anholt2020-05-013-14/+45
| | | | | | | | | | | | We weren't filling in the tess mode of the key, or setting has_gs on GS shaders, resulting in assertion failures when NIR intrinsics didn't get lowered. We have to make a guess at prim mode for TCS, but it should be better to have some shader-db coverage than none, and it will avoid these failures happening when we start precompiling shaders. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Skip tess epilogue if the program is missing stores.Eric Anholt2020-05-011-0/+3
| | | | | | | | Some of the negative API tests make shaders for tess stages that don't do all the stores they need to. Once we start precompiling (or doing shader-db of tess), we need to at least not segfault when generating them. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno: Stop doing binning shaders other than the VS in shader-db.Eric Anholt2020-05-011-1/+1
| | | | | | ir3_cache.c only ever asks for binning variants for VS. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Fix register allocation assertion failures.Eric Anholt2020-05-013-21/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were failing to tell the allocator about the restriction that scalar texture instructions (allocated as scalar regs) couldn't be allocated such that the start of the full unwritemasked vector started before r0. There was a patch in select_reg_callback on a6xx that tried to work around that, but you could still end up backed into a corner you shouldn't be because we didn't tell the RA what it needed. Fixes compiler assertion failures on a300-a400's blit_z shader, used for Z32F gmem blits. Looks like as a result we get tighter register allocation but more nops: instructions in affected programs: 757945 -> 760356 (0.32%) nops in affected programs: 317983 -> 320468 (0.78%) non-nops in affected programs: 27525 -> 27451 (-0.27%) mov in affected programs: 3098 -> 3023 (-2.42%) dwords in affected programs: 109664 -> 110656 (0.90%) last-baryf in affected programs: 112701 -> 112847 (0.13%) full in affected programs: 4326 -> 4011 (-7.28%) sstall in affected programs: 120550 -> 120836 (0.24%) (ss) in affected programs: 13939 -> 13918 (-0.15%) (sy) in affected programs: 3006 -> 2786 (-7.32%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Drop hack to clean up split varsKristian H. Kristensen2020-05-011-24/+0
| | | | | | | | | When the GS lowering was working on store_output intrinsics, we had to clean up the split vars to avoid getting confused. Now that we shadow the output vars instead, there's no confusion and we can drop this hack. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Lower GS builtins before lowering IOKristian H. Kristensen2020-05-014-61/+64
| | | | | | | | | | | | | We mostly got away with replacing a store_output with a store_var, but for complex types like structs, that doesn't work. Once the IO has been lowered from vars to intrinsic, we've lost the deref chains and can't properly shadow the outputs. This commits moves the GS lowering up so we do it before the output variables get lowered to store_output. This way the pass works much like nir_lower_io_to_temporaries() and cleanly shadows the outputs. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Add ir3_nir_lower_to_explicit_input() passKristian H. Kristensen2020-05-013-46/+65
| | | | | | | | | | This pass lowers per-vertex input intrinsics to load_shared_ir3. This was open coded in the TCS and GS lowering passes before - this way we can share it. Furthermore, we'll need to run the rest of the GS lowering earlier (before lowering IO) so we need to split off this part that operates on the IO intrinsics first. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Rename ir3_nir_lower_to_explicit_ioKristian H. Kristensen2020-05-013-6/+6
| | | | | | | We rename it to ir3_nir_lower_to_explicit_output, since it only handles output and we'll add a lowering pass for input next. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Pass stream output info to ir3_shader_from_nirKristian H. Kristensen2020-05-013-5/+10
| | | | | | | | We need shader->stream_output filled out when we layout the push constants in ir3_setup_const_state(). Otherwise const_state->offsets.tfbo ends up as ~0, which doesn't work. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Fix the a3xx TF outputs stores.Eric Anholt2020-05-011-1/+1
| | | | | | | We were trying to deref the vector-collected outputs[] array before it's been set up, but we want the per-component outputs anyway. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno/ir3: Set up the block predecessors for a3xx TFEric Anholt2020-05-012-2/+8
| | | | | | Fixes a segfault in ir3_legalize. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* intel/fs: Update location of Render Target Array Index for gen12D Scott Phillips2020-05-011-1/+9
| | | | | | | | | | | | Render Target Array Index has moved from R0.0[26:16] to R1.1[26:16] on gen12. Fixes dEQP-VK.multiview.input_attachments.* Cc: <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4836>
* pan/decode: Properly print tripped zeroesTomeu Vizoso2020-05-011-1/+1
| | | | | | | | | The "%" got lost. Signed-off-by: Tomeu Vizoso <[email protected]> Fixes: 6148d1be4bb5 ("panfrost: Fix size of bifrost sampler descriptor") Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* panfrost: Add Bifrost texture trampoline BO to batchTomeu Vizoso2020-05-011-0/+6
| | | | | | | Fixes: d3eb23adb50c ("panfrost: Emit sampler descriptor on bifrost") Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* pan/bi: Lower for now sincosAlyssa Rosenzweig2020-05-011-0/+1
| | | | | | | | | Will be implemented later. Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* panfrost: mali_attr_meta.unknown1 is zero on BifrostTomeu Vizoso2020-05-011-1/+1
| | | | | | | | For unknown1 reasons :) Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* panfrost: GPUs newer than G-71 don't have swizzles...Tomeu Vizoso2020-05-015-8/+47
| | | | | | | | for attributes and varyings. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* pan/decode: Trace to stderr with PANDECODE_DUMP_FILE=stderrTomeu Vizoso2020-05-011-18/+16
| | | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* panfrost: Update Bifrost fields in mali_shader_metaAlyssa Rosenzweig2020-05-011-3/+12
| | | | | | | | | | | Not much is known currently about these fields and their values, but this gets things going in the scenarios we have been testing with so far. Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* pan/bi: Print shaders only if BIFROST_MESA_DEBUG=shadersTomeu Vizoso2020-05-012-4/+34
| | | | | | | | Similar to how it's done in the Midgard compiler. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* pan/bi: Enable lower_mediump_outputs NIR passAlyssa Rosenzweig2020-05-011-0/+1
| | | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
* panfrost: Add a bit more info about some tiler fieldsTomeu Vizoso2020-05-012-7/+10
| | | | | | | | | | | | | | | Has been observed that after the job chain has completed, those fields become populated. tiler_heap_next_start contains an address inside the tiler heap, a bit before the value that the GPU writes to tiler_heap_free. used_hierarchy_mask contains a hex value that corresponds to values observed as hierarchy masks. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4832>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 13:42:06 +0000