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* radeonsi: add SWITCH_ON_EOI requirement for 4 SE partsMarek Olšák2015-10-241-0/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unnecessary PARTIAL_VS_WAVE setting for streamoutMarek Olšák2015-10-241-4/+0
| | | | | | hardware does this automatically Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: allow unbinding vertex shadersMarek Olšák2015-10-241-2/+2
| | | | | | Draw calls without a vertex shader are skipped. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: allow unbinding pixel shaders and remove the dummy shaderMarek Olšák2015-10-243-22/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add draw_vbo check for a NULL pixel shaderMarek Olšák2015-10-243-1/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add checks for a NULL pixel shaderMarek Olšák2015-10-242-32/+42
| | | | | | This will allow removing the dummy PS. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/util: add a test for NULL fragment shadersMarek Olšák2015-10-241-0/+38
| | | | | | Just to validate that radeonsi doesn't crash. Reviewed-by: Michel Dänzer <[email protected]>
* st/mesa: don't load state parameters if there are noneMarek Olšák2015-10-241-1/+2
| | | | | | | | | Out of 7063 shaders from my shader-db: - 6564 (93%) shaders don't have any state parameters. - 347 (5%) shaders have 1 state parameter for WPOS lowering. - The remaining 2% have more state parameters, usually matrices. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: add Stoney pci idsSamuel Li2015-10-231-0/+2
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeonsi: add support for Stoney asics (v3)Samuel Li2015-10-235-3/+19
| | | | | | | | | | | v2 (agd): rebase on mesa master, split pci ids to separate commit v3 (agd): use carrizo for llvm processor name for llvm 3.7 and older Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* nvc0: respect edgeflag attribute widthIlia Mirkin2015-10-231-7/+33
| | | | | | | | | | | | The edgeflag comes in as ubyte with glEdgeFlagPointer but as float with plain immediate glEdgeFlag. Avoid reading bytes that weren't meant for the edgeflag in the pointer case. Fixes intermittent failures with gl-2.0-edgeflag piglit (and valgrind complaints about reading uninitialized memory). Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gallivm: Explicitly disable unsupported CPU features.Jose Fonseca2015-10-231-38/+34
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92214 CC: "10.6 11.0" <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* vc4: Convert blending to being done in 4x8 unorm normally.Eric Anholt2015-10-235-51/+276
| | | | | | | | | | | | | We can't do this all the time, because you want blending to be done in linear space, and sRGB would lose too much precision being done in 4x8. The win on instructions is pretty huge when you can, though. total uniforms in shared programs: 32065 -> 32168 (0.32%) uniforms in affected programs: 327 -> 430 (31.50%) total instructions in shared programs: 92644 -> 89830 (-3.04%) instructions in affected programs: 15580 -> 12766 (-18.06%) Improves openarena performance at 1920x1080 from 10.7fps to 11.2fps.
* vc4: Add QIR/QPU support for the 8-bit vector instructions.Eric Anholt2015-10-234-0/+45
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* vc4: Don't try to CSE non-SSA instructions.Eric Anholt2015-10-231-0/+1
| | | | | | | This can happen when we're doing destination packing -- we don't know what's in the rest of the register. Signed-off-by: Eric Anholt <[email protected]>
* nir: Add opcodes for saturated vector math.Eric Anholt2015-10-232-0/+51
| | | | | | | | | This corresponds to instructions used on vc4 for its blending inside of shaders. I've seen these opcodes on other architectures before, but I think it's the first time these are needed in Mesa. v2: Rename to 'u' instead of 'i', since they're all 'u'norm (from review by jekstrand)
* vc4: Add dumping of VC4_PACKET_GL_INDEXED_PRIMITIVE.Eric Anholt2015-10-231-1/+22
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* vc4: Add a workaround for HW-2116 (state counter wrap fails).Eric Anholt2015-10-233-6/+40
| | | | | | I haven't proven that this happens (I've got other GPU hangs in the way), but the closed driver also does this and it's documented as an errata.
* vc4: Fix missing \n in a perf_debug().Eric Anholt2015-10-231-1/+1
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* i965/fs: Allow copy propagating into new surface access opcodesKristian Høgsberg Kristensen2015-10-231-0/+15
| | | | | Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Optimize ssbo storesKristian Høgsberg Kristensen2015-10-231-30/+25
| | | | | | | Reviewed-by: Francisco Jerez <[email protected]> Write groups of enabled components together. Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Drop offset_reg temporary in ssbo loadKristian Høgsberg Kristensen2015-10-231-5/+3
| | | | | | | | | | Now that we don't read each component one-by-one, we don't need the temoprary vgrf for the offset. More importantly, this register was type UD while the nir source was type D. This broke copy propagation and left a redundant MOV in the generated code. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Avoid scalar destinations in emit_uniformize()Kristian Høgsberg Kristensen2015-10-231-4/+11
| | | | | | | | | The scalar destination registers break copy propagation. Instead compute the results to a regular register and then reference a component when we later use the result as a source. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Don't uniformize surface index twiceKristian Høgsberg Kristensen2015-10-231-2/+0
| | | | | | | | The emit_untyped_read and emit_untyped_write helpers already uniformize the surface index argument. No need to do it before calling them. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Use unsigned immediate 0 when eliminating ↵Kristian Høgsberg Kristensen2015-10-231-1/+1
| | | | | | | | | | | | SHADER_OPCODE_FIND_LIVE_CHANNEL The destination for SHADER_OPCODE_FIND_LIVE_CHANNEL is always a UD register. When we replace the opcode with a MOV, make sure we use a UD immediate 0 so copy propagation doesn't bail because of non-matching types. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/fs: Read all components of a SSBO field with one sendKristian Høgsberg Kristensen2015-10-231-18/+7
| | | | | | | | | Instead of looping through single-component reads, read all components in one go. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965: Don't use message headers for untyped readsKristian Høgsberg Kristensen2015-10-232-3/+2
| | | | | | | | | | | | We always set the mask to 0xffff, which is what it defaults to when no header is present. Let's drop the header instead. v2: Only remove header for untyped reads. Typed reads always need the header. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965/vec4: check opcode on vec4_instruction::reads_flag(channel)Alejandro Piñeiro2015-10-231-2/+2
| | | | | | | | | | | | | | Commit f17b78 added an alternative reads_flag(channel) that returned if the instruction was reading a specific channel flag. By mistake it only took into account the predicate, but when the opcode is VS_OPCODE_UNPACK_FLAGS_SIMD4X2 there isn't any predicate, but the flag are used. That mistake caused some regressions on old hw. More information on this bug: https://bugs.freedesktop.org/show_bug.cgi?id=92621 Reviewed-by: Kenneth Graunke <[email protected]>
* vc4: Use Rob's NIR-based user clip lowering.Eric Anholt2015-10-234-69/+14
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* vc4: Also dump the decimation mode for resolved stores.Eric Anholt2015-10-231-2/+4
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* vc4: Use VC4_GET_FIELD and other defines in dumping VC4_RENDER_CONFIG.Eric Anholt2015-10-231-10/+10
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* vc4: Add a sentinel after simulator buffers for buffer overflow detection.Eric Anholt2015-10-231-1/+11
| | | | | | | | | This is a little bit like the mprotect-based fencing I've experimented with, but it's simple and low overhead. The downside is that only catches writes, not reads. It didn't catch any bad writes on a current piglit run, but may be useful in the future.
* glsl: fix shader storage block member rules when adding program resourcesSamuel Iglesias Gonsalvez2015-10-231-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f24e5e did not take into account arrays of named shader storage blocks. Fixes 20 dEQP-GLES31.functional.ssbo.* tests: dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.shared_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.packed_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.std140_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.std430_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.shared_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.packed_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.std140_instance_array dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.std430_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.shared_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.packed_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.std140_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.std430_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.shared_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.packed_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.std140_instance_array dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.std430_instance_array dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.2 dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.29 dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.33 dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.3 V2: - Rename some variables (Timothy) Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ilo: add support for scratch spacesChia-I Wu2015-10-2310-16/+133
| | | | | When a kernel reports a non-zero per-thread scratch space size, make sure the hardware state is correctly set up, and a scratch bo is allocated.
* ilo: fix scratch space setup in coreChia-I Wu2015-10-2311-133/+327
| | | | | | Move scratch_size out of ilo_state_shader_kernel_info and ilo_state_compute_interface_info. A scratch space is shared by all kernels/interfaces. Update builder to emit relocs for scratch bos.
* glsl: remove excess location qualifier validationTimothy Arceri2015-10-231-48/+22
| | | | | | | | | Location has never been able to be a negative value because it has always been validated in the parser. Also the linker doesn't check for negatives like the comment claims. Reviewed-by: Tapani Pälli <[email protected]>
* docs: update relnotes to mention virgl driver.Dave Airlie2015-10-231-0/+1
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* virgl/vtest: add vtest driverDave Airlie2015-10-2311-2/+1243
| | | | | | | | | | | | | | | | | | | | | virgl/vtest is a swrast driver that allows the virgl acceleration to be tested without having a virtual machine. The backend has a unix socket server that this connects to. This is run by setting LIBGL_ALWAYS_SOFTWARE=y GALLIUM_DRIVER=virpipe In this mode all renderering is sent over a socket to the remote renderer, and the results are readback and copies to the screen using drisw. This works well enough to develop new features and to help debug. Signed-off-by: Dave Airlie <[email protected]>
* virgl: add driver for virtio-gpu 3D (v2)Dave Airlie2015-10-2329-1/+5928
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | virgl is the 3D acceleration backend for the virtio-gpu shipping with qemu. The 3D acceleration is designed around gallium and TGSI as the virtualisation layer. The backend renderer translates the virgl interface into OpenGL currently. This is the initial import of the driver to mesa. The kernel driver portions are lined up for drm-next. Currently this driver supports up to GL3.3 and some misc extensions if the host driver exposes it. It is planned to iterate the virgl API to new GL levels as mesa host drivers gain features. v2: fix resource tracking across flushes to avoid ->bind hack in mapping. consolidate mapping and waiting code for transfers. use u_range for dirt tracking. handle larger shaders in protocol. include virtgpu_drm.h in mesa for now. add translation layer for gallium tgsi to virgl tgsi. Signed-off-by: Dave Airlie <[email protected]>
* tgsi: try and handle overflowing shaders. (v2)Dave Airlie2015-10-232-3/+9
| | | | | | | | | | This is used to detect error in virgl if we overflow the shader dumping buffers. v2: return a bool. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: add option to dump floats as hex valuesDave Airlie2015-10-233-2/+30
| | | | | | | | | | | This adds support to the parser to accept hex values as floats, and then adds support to the dumper to allow the user to select to dump float as 32-bit hex numbers. This is required to get accurate values for virgl use of TGSI. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: Condition preemptive flush on draw emissionSinclair Yeh2015-10-224-5/+25
| | | | | | | | | | | | | | On ultra high resolution modes, the preemptive flush flag can be set midway through command submission, a condition that cannot be recovered from a flush-retry, causing rendering artifacts. This patch prevents a preemtive_flush until a draw has been emitted. Signed-off-by: Sinclair Yeh <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: try to avoid index generation for some primitive typesBrian Paul2015-10-221-0/+14
| | | | | | | | | | The svga device doesn't directly support quads, quad strips or polygons so we have to convert those types to indexed triangle lists. But we can sometimes avoid that if we're drawing flat/constant-colored prims and we don't have to worry about provoking vertex. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* svga: avoid provoking vertex conversion when possibleBrian Paul2015-10-221-1/+14
| | | | | | | | | | | | Provoking vertex comes into play when doing flat shading. But if we know that all fragments in a primitive are the same color, the provoking vertex doesn't matter. Check for that case and use whichever provoking vertex convention is supported by the device. This avoids generating an index buffer to do the PV conversion. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* svga: detect constant color writes in fragment shadersBrian Paul2015-10-225-2/+77
| | | | | | | | | | | | | | | | | | Examine the fragment shader to try to detect TGSI shaders which use "MOV OUT[0], CONST[i]" to write a constant value for the fragment color. In this case, all fragments will have the same color (unless blending is enabled). This is a common case for OpenGL code such as: glColor(), glBegin(), glVertex(), ..., glEnd() when lighting/fog/etc are disabled. In this case, the Mesa/gallium state tracker actually generates a simple "MOV OUT[0], CONST[i]" fragment shader. This will be used by the next commit to avoid provoking vertex conversion (creating/rewriting an index buffer) when drawing flat-shaded primitives. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* mesa: check for unchanged line width before error checkingBrian Paul2015-10-221-3/+4
| | | | Reviewed-by: Matt Turner <[email protected]>
* st/mesa: use _mesa_RasterPos() when possibleBrian Paul2015-10-221-0/+10
| | | | | | | | | | | | | | | The st_RasterPos() function goes to great pains to implement the rasterpos transformation. It basically uses gallium's draw module to execute the vertex shader to draw a point, then capture that point's attributes. But glRasterPos isn't typically used with a vertex shader so we can usually use the old/fixed-function implementation which is a lot simpler and faster. This can add up for legacy apps that make a lot of calls to glRasterPos. Reviewed-by: Roland Scheidegger <[email protected]>
* tnl: remove t_rasterpos.cBrian Paul2015-10-222-479/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* drivers/common: use _mesa_RasterPos instead of _tnl_RasterPosBrian Paul2015-10-221-1/+2
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: copy rasterpos evaluation code into core MesaBrian Paul2015-10-222-0/+444
| | | | | | | We'll remove it from the tnl module next. By lifting this code into core Mesa we can use it from the gallium state tracker. Reviewed-by: Roland Scheidegger <[email protected]>
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