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* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
* radv: add missing meson c++ visibility argumentsEric Engestrom2018-10-091-0/+1
* gbm: Add GBM_FORMAT_ARGB1555 supportMichel Dänzer2018-10-091-0/+4
* st/dri: Handle BGRA5551 formatMichel Dänzer2018-10-091-0/+13
* freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark2018-10-081-1/+1
* freedreno/a6xx: add LRZ supportRob Clark2018-10-088-132/+104
* freedreno: update generated headersRob Clark2018-10-087-38/+120
* freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark2018-10-085-38/+30
* freedreno/a6xx: remove unused fxnsRob Clark2018-10-082-19/+0
* freedreno/a6xx: remove fd6_shader_stateobjRob Clark2018-10-083-23/+10
* glsl: fix array assignments of a swizzled vectorIlia Mirkin2018-10-081-3/+10
* radv: tidy up radv_pipeline_init_multisample_state()Samuel Pitoiset2018-10-081-19/+16
* radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARKSamuel Pitoiset2018-10-081-2/+2
* radv: set DB_EQAA.INCOHERENT_EQAA_READSSamuel Pitoiset2018-10-081-1/+1
* i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOESChystiakov, Dmytro2018-10-081-26/+37
* glsl: do not attempt assignment if operand type not parsed correctlyTapani Pälli2018-10-081-0/+6
* util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák2018-10-064-2/+20
* radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák2018-10-061-1/+1
* ac: add ac_build_roundMarek Olšák2018-10-064-6/+20
* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-067-15/+22
* ac: simplify LLVM alloca helpersMarek Olšák2018-10-061-7/+4
* ac: define all address spaces properlyMarek Olšák2018-10-065-14/+16
* gallivm: Make it possible to disable some optimization shortcuts in release b...Gert Wollny2018-10-064-21/+32
* virgl: Pass resource size and transfer offsetsTomeu Vizoso2018-10-064-28/+208
* virgl, vtest: Correct the transfer size calculationGert Wollny2018-10-061-1/+3
* util: Make xmlconfig.c build on Solaris without d_type in dirent (v2)Alan Coopersmith2018-10-051-0/+8
* radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang2018-10-054-2/+18
* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
* radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák2018-10-051-22/+12
* radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang2018-10-055-10/+37
* spirv: mark variables decorated with XfbBuffer as always activeSamuel Pitoiset2018-10-051-0/+1
* docs: update calendar, add news and link release notes to 18.2.2Juan A. Suarez Romero2018-10-053-7/+8
* docs: add sha256 checksums for 18.2.2Juan A. Suarez Romero2018-10-051-1/+2
* docs: add release notes for 18.2.2Juan A. Suarez Romero2018-10-051-0/+154
* nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansionsJason Ekstrand2018-10-041-15/+18
* glsl/linker: Check the subroutine associated functions namesVadym Shovkoplias2018-10-041-0/+40
* virgl: Negotiate version with vtest serverTomeu Vizoso2018-10-043-0/+64
* intel: aubinator: Fix memory leaksSagar Ghuge2018-10-041-0/+25
* intel/decoder: construct correct xml filenameSagar Ghuge2018-10-041-8/+7
* intel/decoder: Avoid freeing invalid pointerSagar Ghuge2018-10-041-5/+13
* intel/decoder: add gen_spec_init methodSagar Ghuge2018-10-041-16/+35
* radv: fix resetting the pool for timestamp queriesSamuel Pitoiset2018-10-041-7/+5
* etnaviv: Use write combine instead of unached mappings for shader boGuido Günther2018-10-041-1/+1
* drirc: add a workaround for ARMA 3Marek Olšák2018-10-041-0/+4
* anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_STARTJason Ekstrand2018-10-031-0/+9
* anv: Use separate MOCS settings for external BOsJason Ekstrand2018-10-0312-38/+80
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