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* intel/isl: Plumb devinfo into isl_genX(buffer_fill_state_s)Jason Ekstrand2020-01-243-3/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
* intel/disasm: Properly disassemble indirect SENDsJason Ekstrand2020-01-241-3/+16
| | | | | | | | Instead of emitting g[a0]UD for the indirect descriptor, emit a0<0>UD. This is more correct because there is no GRF involved. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
* intel/fs: Don't unnecessarily fall back to indirect sends on Gen12Jason Ekstrand2020-01-241-3/+4
| | | | | | | | | | The instruction encoding for SENDS changed on Gen12 and it now supports embedding the entire extended message descriptor in the instruction if it's an immediate. Stop falling back to doing an indirect SEND just because we had something in [15:12] of ex_desc.ud. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
* anv: Improve BTI change cache flushingJason Ekstrand2020-01-242-7/+17
| | | | | | | | | | | | | | | This commit makes two changes: 1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly for the flush at the end of cmd_buffer_begin_subpass. 2. Because BLORP ops such as vkCmdClearAttachments may come in the middle of a render pass, we have to also flag the need for a cache flush after the blorp op. Fixes: 185630c6bc97 "anv/blorp: Do the gen11 BTI flush" Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
* panfrost: Fix 32-bit warning for `indices`Alyssa Rosenzweig2020-01-241-1/+1
| | | | | | | | | | | | ../src/gallium/drivers/panfrost/pan_context.c: In function ‘panfrost_draw_vbo’: ../src/gallium/drivers/panfrost/pan_context.c:1551:70: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = (u64) NULL; ^ Signed-off-by: Alyssa Rosenzweig <[email protected]> Reported-by: Icecream95 <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* pan/decode: Remove SHORT_SLIDE indirectionAlyssa Rosenzweig2020-01-241-15/+6
| | | | | | | | | | | | | ../src/panfrost/pandecode/decode.c: In function ‘pandecode_compute_fbd’: ../src/panfrost/pandecode/decode.c:789:35: warning: taking address of packed member of ‘struct mali_compute_fbd’ may result in an unaligned pointer value [-Waddress-of-packed-member] 789 | pandecode_u32_slide(num, s->unknown ## num, ARRAY_SIZE(s->unknown ## num)) | ~^~~~~~~~~ ../src/panfrost/pandecode/decode.c:800:9: note: in expansion of macro ‘SHORT_SLIDE’ 800 | SHORT_SLIDE(1); | ^~~~~~~~~~~ Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* pan/midgard: Remove pack_color defineAlyssa Rosenzweig2020-01-241-1/+0
| | | | | | | | | | | | | | | | | Unused at the moment. ../src/panfrost/midgard/midgard_compile.c:124:29: warning: ‘m_pack_colour’ defined but not used [-Wunused-function] 124 | static midgard_instruction m_##name(unsigned ssa, unsigned address) { \ | ^~ ../src/panfrost/midgard/midgard_compile.c:145:22: note: in expansion of macro ‘M_LOAD_STORE’ 145 | #define M_LOAD(name) M_LOAD_STORE(name, false) | ^~~~~~~~~~~~ ../src/panfrost/midgard/midgard_compile.c:213:1: note: in expansion of macro ‘M_LOAD’ 213 | M_LOAD(pack_colour); | ^~~~~~ Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* pan/decode: Remove last_sizeAlyssa Rosenzweig2020-01-241-4/+0
| | | | | | | | | Fixes ../src/panfrost/pandecode/decode.c: In function ‘pandecode_jc’: ../src/panfrost/pandecode/decode.c:2859:14: warning: variable ‘last_size’ set but not used [-Wunused-but-set-variable] 2859 | bool last_size; Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* panfrost: Don't use implicit mali_exception_status enumAlyssa Rosenzweig2020-01-242-2/+2
| | | | | | | Fixes ../src/panfrost/pandecode/public.h:53:33: warning: ‘enum mali_exception_access’ declared inside parameter list will not be visible outside of this definition or declaration Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* radv: enable ACO support for GFX6Samuel Pitoiset2020-01-241-4/+0
| | | | | | | | | | | | | | | | | | | | | | | CTS should pass, as well as Crucible and the few number of Piglit tests. List of game benchmarks tested: - Dawn of War 3 - Serious Sam 2017 - Shadow of The Tomb Raider - The Talos Principle - Thrones of Britannia - Total Warhammer 2 - Total War: Three Kingdoms Note that F12017 hangs with or without ACO on GFX6 at the moment. My whole pipelinedb (~30 games) doesn't trigger any compiler crashes. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2401 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
* aco: copy the literal offset of SMEM instructions to a temporarySamuel Pitoiset2020-01-241-5/+10
| | | | | | | | | | GFX6 only supports up to 8-bit for the literal offset, so make sure it's copied to a temporary SGPR before emitting a SMEM instruction. The optimizer will propagate the literal offset if possible anyways. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
* aco: fix a hazard with v_interp_* and v_{read,readfirst}lane_* on GFX6Samuel Pitoiset2020-01-242-0/+27
| | | | | | | | | | | | | It's required to insert 1 wait state if the dst VGPR of any v_interp_* is followed by a read with v_readfirstlane or v_readlane to fix GPU hangs on GFX6. Note that v_writelane_* is apparently not affected. This hazard isn't documented anywhere but AMD confirmed it. This fixes a GPU hang with the texturemipmapgen Sascha demo on GFX6. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
* aco: fix a hardware bug for MRTZ exports on GFX6Samuel Pitoiset2020-01-241-0/+9
| | | | | | | | | GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X writemask component. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3533>
* turnip: Implement vkCmdCopyQueryPoolResults for occlusion queriesBrian Ho2020-01-241-0/+111
| | | | | | | | | Use CP_COND_EXEC and CP_COND_WRITE to conditionally copy the results of a query to a buffer based off the query's availability. Fixes: #2238 Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Implement vkCmdResetQueryPoolBrian Ho2020-01-241-0/+38
| | | | | | Clears the available bit for each requested query on the GPU. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Implement vkGetQueryPoolResults for occlusion queriesBrian Ho2020-01-241-0/+125
| | | | | | | | Implements fetching the results of a query pool with the VK_QUERY_RESULT_WAIT_BIT, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT, and VK_QUERY_RESULT_PARTIAL_BIT flags. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Update query availability on render pass endBrian Ho2020-01-244-9/+44
| | | | | | | | | | | | | | Unlike on an immidiate-mode renderer, Turnip only renders tiles on vkCmdEndRenderPass. As such, we need to track all queries that were active in a given render pass and defer setting the available bit on those queries until after all tiles have rendered. This commit adds a draw_epilogue_cs to tu_cmd_buffer that is executed as an IB at the end of tu_CmdEndRenderPass. We then emit packets to this command stream that update the availability bit of a given query in tu_CmdEndQuery. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Implement vkCmdEndQuery for occlusion queriesBrian Ho2020-01-241-0/+82
| | | | | | | | | Mostly a translation of freedreno's implementation of glEndQuery for GL_SAMPLES_PASSED query objects with a slight modification to set the availability bit of the query bo (slot->available) if the query was not ended inside a render pass. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Implement vkCmdBeginQuery for occlusion queriesBrian Ho2020-01-241-0/+68
| | | | | | | | Mostly a translation of freedreno's implementation of glBeginQuery for GL_SAMPLES_PASSED query objects with special logic for handling tiled render passes. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Implement vkCreateQueryPool for occlusion queriesBrian Ho2020-01-241-0/+52
| | | | | | | | | General structure is inspired by anv's implementation in genX_query.c. We define a packed struct that tracks sample count at the beginning of the query and at the end; the result of the occlusion query is then slot->end - slot->begin. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* turnip: Update tu_query_pool with turnip-specific fieldsBrian Ho2020-01-241-4/+3
| | | | | | | tu_query_pool was forked from radv_query_pool, but we will need a different set of fields to implement queries in turnip. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3279>
* anv: Allow HiZ in read-only depth layoutsJason Ekstrand2020-01-241-0/+60
| | | | | | | | This improves the performance of Aztec Ruins by 5% on ICL. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
* anv: Add a usage parameter to anv_layout_to_aux_usageJason Ekstrand2020-01-244-18/+53
| | | | | | | | | | | | | | | | | Most places we actually know the usage and can provide it. There are two exceptions to this: 1. We pass 0 into get_blorp_surf_for_anv_image when we use ANV_IMAGE_LAYOUT_EXPLICIT_AUX because anv_layout_to_aux_usage is never actually called so it doesn't matter. 2. We pass 0 into anv_layout_to_aux_usage in transition_color_buffer. However, the coming commits which will begin using the usage parameter only care about depth. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
* anv: Use isl_aux_state for HiZ resolvesJason Ekstrand2020-01-242-19/+50
| | | | | | | | | | | | Rather than looking at the aux usage, we look at the isl_aux_state which provides us with more detailed information. This commit adds a couple helpers to isl which let us quickly determine if we have valid depth/hiz on the initial layout and if we need valid depth/hiz for the final layout. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
* anv: Add a layout_to_aux_state helperJason Ekstrand2020-01-242-82/+134
| | | | | | | | | | | This new helper maps VkImageLayout enums to isl_aux_state enums which are the hardware's concept of image layouts. We can then use the aux state to get the fast clear type and the aux usage. This should yield no functional change in driver behavior. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
* anv: Use TRANSFER_SRC_OPTIMAL for depth/stencil MSAA resolvesJason Ekstrand2020-01-241-4/+4
| | | | | | | | | | | | As of 52ad1712ed62, TRANSFER_SRC_OPTIMAL and SHADER_READ_ONLY_OPTIMAL are now identical for depth buffers so there's no reason why we need to use the "wrong" layout. Technically, according to Vulkan, blits and MSAA resolves are transfer ops so we should use the transfer layout now that we can. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2605>
* intel/blorp: resize src and dst surfaces separatelyJason Ekstrand2020-01-241-45/+53
| | | | | | | | | | | | | | | When copying to an RGB surface, we treat it as an R only one of three times the width, which may end up being larger than the maximum size supported by the hardware and so it hits the shrink path. This forced both source and destination surfaces to be shrunk, even though it's not necessary for the former, and may even hit some assertions in some cases, such as the surface being compressed. Fixes several tests under dEQP-VK.api.copy_and_blit.core.image_to_image.dimensions.* Reviewed-by: Jordan Justen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3422>
* aco: combine MRTZ (depth, stencil, sample mask) exportsSamuel Pitoiset2020-01-242-280/+259
| | | | | | | | | | | | | | | | | | | | | | Instead of emitting up to 3 for each different components (depth, stencil and sample mask). This is needed to fix a hw bug on GFX6. Totals from affected shaders: SGPRS: 34728 -> 35056 (0.94 %) VGPRS: 26440 -> 26476 (0.14 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 1346088 -> 1344180 (-0.14 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 3922 -> 3915 (-0.18 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3538>
* aco/gfx10: Fix VcmpxExecWARHazard mitigation.Timur Kristóf2020-01-242-3/+2
| | | | | | | | | | | | | The SOPP instruction shouldn't have a definition, and its block should be set to -1 in order to prevent it from being recognized as a branch. Also fix a typo in the readme. Fixes: d6dfce02d074d615a3b88a3fccd8ee8c7e13c010 Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3552>
* aco: Transform uniform bitwise instructions to 32-bit if possible.Timur Kristóf2020-01-241-0/+87
| | | | | | | | | | | | | | | | | | This allows removing superfluous s_cselect instructions that come from turning booleans into 64-bit vector condition. v2 by Daniel Schürmann: - Make the code massively simpler v3 by Timur Kristóf: - Fix regressions, make it work in wave32 mode - Eliminate extra moves by not always using the SCC definition - Use s_absdiff_i32 for uniform XOR - Skip the transformation for uncommon or invalid instructions Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3450>
* etnaviv: update Android build filesMartin Fuzzey2020-01-248-2/+92
| | | | | | | | | etnaviv no longer builds on Android, fix this. Signed-off-by: Martin Fuzzey <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
* aco: use nir_move_copiesRhys Perry2020-01-241-1/+2
| | | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* radv/aco: use ACO for GS copy shadersRhys Perry2020-01-243-4/+7
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: implement GS copy shadersRhys Perry2020-01-244-148/+327
| | | | | | | | | v5: rebase on float_controls changes v7: rebase after shader args MR and load/store vectorizer MR Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: remove needs_instance_idRhys Perry2020-01-242-6/+0
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: explicitly mark end blocks for exportsRhys Perry2020-01-243-12/+8
| | | | | | | | | | | | | For GS copy shaders, whether we want to do exports is conditional. By explicitly marking the end blocks, we can mark an IF's then branch as an export block and ensure that's where the assembler inserts null exports. v6: only fixup exports in the end block, like before v8: simplify some code Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* radv/aco: allow ACO for GSRhys Perry2020-01-241-8/+9
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: implement GS on GFX7-8Rhys Perry2020-01-244-69/+186
| | | | | | | | | | | GS is the same on GFX6, but GFX6 isn't fully supported yet. v4: fix regclass v7: rebase after shader args MR Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* radv/aco,aco: implement GS on GFX9+Rhys Perry2020-01-249-141/+523
| | | | | | | | | | | | | | | | | v2: implement GFX10 v3: rebase v7: rebase after shader args MR v8: fix gs_vtx_offset usage on GFX9/GFX10 v8: use unreachable() instead of printing intrinsic v8: rename output_state to ge_output_state v8: fix formatting around nir_foreach_variable() v8: rename some helpers in the scheduler v8: rename p_memory_barrier_all to p_memory_barrier_common v8: fix assertion comparing ctx.stage against vertex_geometry_gs Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: improve support for s_sendmsgRhys Perry2020-01-244-2/+79
| | | | | | | | In particular, the messages needed for GS. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* radv: move gs copy shader creation before other variantsRhys Perry2020-01-241-36/+36
| | | | | | | | | | | | ACO lowers output derefs which breaks the shader_info pass used by gs copy shader creation. v3: rebase Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2421>
* aco: Make a better guess at which instructions need the VCC hint.Timur Kristóf2020-01-242-1/+17
| | | | | | | | | | | Previously, bool_to_vector_condition would always set the VCC hint on its result. This commit improves it by having the optimizer set the VCC hint only when the result really needs to be in the VCC. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3451>
* gallium/swr: implementation of tessellation shaders compilationJan Zielinski2020-01-2416-47/+1885
| | | | | | | | | | | | TCS and TES shaders compilation mechanisms in SWR and state management implementation. Reviewed-by: Krzysztof Raszkowski <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]> Acked-by: Roland Scheidegger <[email protected]> Acked-by: Dave Airlie <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
* radv: Allow DCC & TC-compat HTILE with VK_IMAGE_CREATE_EXTENDED_USAGE_BIT.Bas Nieuwenhuizen2020-01-241-4/+2
| | | | | | | | | | | | I misunderstood the flag when initially disabling. But this flag only does something with mutable formats. If we have DCC and mutable formats, the formats are close enough that the allowed usage flags are not meaningfully different nor used during allocation. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3424>
* radv: Expose VK_KHR_swapchain_mutable_format.Bas Nieuwenhuizen2020-01-243-1/+3
| | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2354 Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3425>
* freedreno: Document CP_INDIRECT_BUFFER_CHAINConnor Abbott2020-01-241-0/+6
| | | | | | | | | This will let us use batch chaining instead of growing batches on a5xx and a6xx. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
* freedreno: Document CP_UNK_A6XX_55Connor Abbott2020-01-242-23/+62
| | | | | Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
* freedreno: Document CP_COND_REG_EXEC moreConnor Abbott2020-01-243-13/+40
| | | | | | | | | The vulkan blob uses the RENDER_MODE mode to condition a blit on the render mode in traces of a dEQP triangle test. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
* ac/llvm: fix missing casts in ac_build_readlane()Samuel Pitoiset2020-01-241-6/+9
| | | | | | | | | | | | | | | | | | | | | | | Because ac_build_optimization_barrier() overwrites the original src_type, we have to keep track of it before emitting that barrier. Otherwise, wrong conversions are expected for pointers or small bitsizes. By doing this, we no longer need to do the cast dance in ac_build_readlane_no_opt_barrier(), it was just necessary for ac_build_optimization_barrier(). This fixes a bunch of crashes with subgroups related tests when RADV_DEBUG=checkir is enabled, and it also fixes a compiler crash with The Surge 2. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2395 Fixes: 0f45d4dc2b1 ("ac: add ac_build_readlane without optimization barrier") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3535>
* anv/apply_pipeline_layout: Initialize the nir_builder before useJason Ekstrand2020-01-231-1/+2
| | | | | | | Fixes: #2410 Fixes: 3c754900b5f "nir: don't emit ishl in _nir_mul_imm() if backend doesn't support bitops" Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3548>
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