| Commit message (Collapse) | Author | Age | Files | Lines |
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v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <[email protected]>
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Reviewed-by: Topi Pohjolainen <[email protected]>
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v2: Drop VEC4 suport.
v3: Rebase.
v4: Move array coordinate workaround into the surface builder.
Reviewed-by: Jason Ekstrand <[email protected]>
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Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determining the bitfield position of each
component. Most of the remaining functions perform integer, fixed
point normalized, and floating point type conversions, mapping between
a target type with per-component bit widths given by a parameter and a
matching native representation of the same type.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Fix clamping of negative floats in the unsigned case of
emit_convert_to_scaled().
Reviewed-by: Jason Ekstrand <[email protected]>
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Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
v2: Drop VEC4 suport.
v3: Add SKL support.
Reviewed-by: Jason Ekstrand <[email protected]>
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Accounting for the padding required for 1D arrays in certain cases.
Reviewed-by: Jason Ekstrand <[email protected]>
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Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and swizzling. They are still useful
because typed surface reads don't support any 64 or 128-bit formats on
IVB, and they don't support any 128-bit formats on HSW and BDW.
The tiling algorithm is implemented based on a number of parameters
which are passed in as uniforms and determine whether the surface
layout is X-tiled, Y-tiled or untiled. This allows binding surfaces
of different tiling layouts to the pipeline without recompiling the
program.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Add plenty of comments (Jason).
Reviewed-by: Jason Ekstrand <[email protected]>
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These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB and untyped messages elsewhere) we need to
implement it in software to work around lacking hardware support.
v2: Drop VEC4 suport.
v3: Rebase.
Reviewed-by: Jason Ekstrand <[email protected]>
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Reviewed-by: Paul Berry <[email protected]>
v2: Drop VS support pre-Gen8, drop GS support.
Reviewed-by: Kenneth Graunke <[email protected]>
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load/store.
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
Reviewed-by: Kenneth Graunke <[email protected]>
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v2: Set the PS UAV-only bit on HSW (Ken).
Reviewed-by: Kenneth Graunke <[email protected]>
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Shaders with image uniforms may have side effects. Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.
v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
has image uniforms instead of checking core mesa data structures
(Ken).
Reviewed-by: Kenneth Graunke <[email protected]>
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v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <[email protected]>
Acked-by: Jason Ekstrand <[email protected]>
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program.
v2: Add CS support.
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
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This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too. surface_idx
is always used.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
v3: Improve documentation.
Reviewed-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
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v2: Add SKL support.
Reviewed-by: Jason Ekstrand <[email protected]>
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This works as-is on SKL, only the assertion needs to be relaxed.
Reviewed-by: Jason Ekstrand <[email protected]>
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Reviewed-by: Jason Ekstrand <[email protected]>
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Reviewed-by: Thomas Helland <[email protected]>
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Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
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A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: "10.6" <[email protected]>
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Reviewed-by: Matt Turner <[email protected]>
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Reviewed-by: Matt Turner <[email protected]>
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Acked-by: Matt Turner <[email protected]>
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reg_width is kind of an outdated concept.
Reviewed-by: Matt Turner <[email protected]>
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They are never used after the set is finalized so there's no reason to keep
them around.
Reviewed-by: Matt Turner <[email protected]>
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All this commit does is change an early return to an if with an else
clause.
Reviewed-by: Matt Turner <[email protected]>
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Reviewed-by: Matt Turner <[email protected]>
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On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
a boolean negate and not an integer negate. However, NIR's soruce
modifiers are the integer version. We have to resolve it with a MOV prior
to emitting the actual instruction. This is basically the same thing we do
in the FS backend.
Reviewed-by: Matt Turner <[email protected]>
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The analysis code was already there and running, we just weren't doing
anything with the result of it yet.
Reviewed-by: Matt Turner <[email protected]>
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Reviewed-by: Matt Turner <[email protected]>
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Previously, we were explicitly listing every instruction that needs a
resolve. However, those instructions were precicely the ones that returned
booleans so there's no reason why we shouldn't just have that check. Also,
all of the reduction opcodes such as bany and ball were missing so it
didn't properly flag stuff on vec4. If an opcode gets added in the future
that returns a bool but doesn't need a resolve, we can special-case that.
Reviewed-by: Matt Turner <[email protected]>
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This better ensures that the src_bits == dst_bits case gets optimized away.
Reviewed-by: Neil Roberts <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
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v2: just clear the flag before the allocation
Reviewed-by: Michel Dänzer <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <[email protected]>
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For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <[email protected]>
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GLES 3.1 must be allowed to use multisampled framebuffer textures.
Signed-off-by: Marta Lofstedt <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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v3 : Removed space in comment.
Signed-off-by: Marta Lofstedt <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
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This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.
v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style
Signed-off-by: Oded Gabbay <[email protected]>
CC: "10.5 10.6" <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
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More portable. Based on Roland Scheidegger's idea.
Tested with roundevent_test on Linux, MinGW, and MSVC.
https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
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Neither MSVC nor MinGW defines LONG_BIT. For MSVC this was not a problem as
it doesn't define __x86_64__ macro (it's GCC specific.)
However on Windows long type is guaranteed to be 32bits.
Also add an #error, as GCC will just warn, not throw any error, when no
value is returned.
Trivial.
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Fixes build with MinGW x86_64 build with GCC 4.9, due to conflicting
definition _mm_shuffle_epi8 of u_sse.h and system headers.
Trivial.
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To avoid collission with windows.h's PURE macro.
We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.
Reviewed-by: Brian Paul <[email protected]>
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We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.
Fixes: 45e110bad9d (egl/x11: trust our loader over the xserver for the
drivername)
Reported-by: Timothy Arceri <[email protected]>
Signed-off-by: Boyan Ding <[email protected]>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <[email protected]>
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This should have been a part of:
commit 7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <[email protected]>
Date: Wed Jul 29 12:35:24 2015 -0700
i965/skl: Add production thread counts and URB size
Signed-off-by: Ben Widawsky <[email protected]>
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Since the introduction of new gl_shader_stages in
commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <[email protected]>
Date: Fri Mar 7 10:19:09 2014 +0100
mesa: add tessellation shader enums
the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.
Signed-off-by: Chris Wilson <[email protected]>
Cc: Abdiel Janulgue <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Matt Turner <[email protected]>
Cc: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
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