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* i965: Always set AALINEDISTANCE_TRUE on Sandybridge.Kenneth Graunke2017-04-281-2/+1
| | | | | | | | We set this unconditionally on every other platform. Zero (Manhattan) isn't even listed as an option in the Sandybridge docs - only "true". Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Use true AA line distance on G45/Ironlake.Kenneth Graunke2017-04-281-1/+1
| | | | | | | | | | | | | | | | | | The original Broadwater and Crestline platforms computed antialiased line distances using "manhattan" distance, aka a + b = c. Eaglelake and Cantiga added "true" distance, which apparently does something like max(a, b) + min(a, b) / 4. Not exactly "true", but at least more accurate. The G45 documentation indicates that the old manhattan distance setting is "only for debug purposes" and should never be used. The Ironlake documentation no longer mentions AALINEDISTANCE_MANHATTAN, though it does still contain the narrative about the feature. At any rate, we should use the more accurate mode. Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* docs: add news item and link release notes for 17.0.5Andres Gomez2017-04-292-0/+7
| | | | Signed-off-by: Andres Gomez <[email protected]>
* docs: add sha256 checksums for 17.0.5Andres Gomez2017-04-291-1/+2
| | | | | Signed-off-by: Andres Gomez <[email protected]> (cherry picked from commit 6cb65ce2d3689ae7f692f8cf08559109037dd74e)
* docs: add release notes for 17.0.5Andres Gomez2017-04-291-0/+143
| | | | | Signed-off-by: Andres Gomez <[email protected]> (cherry picked from commit 61b134a862ecc1877bbe2f2c14e493b5fb607e04)
* radeonsi: don't load unused compute shader input SGPRs and VGPRsMarek Olšák2017-04-284-48/+76
| | | | | | | | | Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine whether to load BLOCK_ID for each component separately, and set the number of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave rate in most cases. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: record compute shader system value usageMarek Olšák2017-04-282-0/+37
| | | | | | v2: just do indexing with swizzle[i] Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a HUD query for draw calls with primitive restartMarek Olšák2017-04-284-0/+11
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: tell LLVM not to remove s_barrier instructionsMarek Olšák2017-04-281-12/+33
| | | | | | | LLVM 5.0 removes s_barrier instructions if the max-work-group-size attribute is not set. What a surprise. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix tess offchip offset for per-patch attributesMarek Olšák2017-04-283-12/+18
| | | | | | We need 4 more bits there. I don't know what is fixed by this. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: pass tessellation ring addresses via user SGPRsMarek Olšák2017-04-287-56/+112
| | | | | | | | | | | | | | | | | This removes s_load_dword latency for tess rings. We need just 1 SGPR for the address if we use 64K alignment. The final asm for recreating the descriptor is: // s2 is (address >> 16) s_mov_b32 s3, 0 s_lshl_b64 s[4:5], s[2:3], 16 s_mov_b32 s6, -1 s_mov_b32 s7, 0x27fac v2: bitcast the descriptor type from v2i64 to v4i32 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogueMarek Olšák2017-04-281-19/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove VS epilog code, compile VS with PrimID export on demandMarek Olšák2017-04-285-210/+31
| | | | | | | | | | | | The use of PrimID in the pixel shader is too rare to deserve such a sizable support code. The initial idea of the VS epilog was to move the clipping code there and remove it based on states, but optimized variants are now used to do that and are easier to support, so the VS epilog has turned out to be not so useful. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3Marek Olšák2017-04-284-13/+33
| | | | | | VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't load PrimID in TES if it's not usedMarek Olšák2017-04-281-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: explain (non-)monolithic shadersMarek Olšák2017-04-281-0/+67
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: enable OpenGL 4.5Marek Olšák2017-04-281-5/+0
| | | | | | | Tentatively enable it, expecting the scratch buffer support to be done before the next Mesa release. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1stMarek Olšák2017-04-282-10/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add reference counting for shader selectorsMarek Olšák2017-04-282-3/+25
| | | | | | | The 2nd shader of merged shaders should take a reference of the 1st shader. The next commit will do that. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GSMarek Olšák2017-04-281-6/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set TES registers for merged ES-GSMarek Olšák2017-04-281-4/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GSMarek Olšák2017-04-281-0/+10
| | | | | | not implemented yet Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: always compile monolithic ES-GS (asynchronously)Marek Olšák2017-04-282-1/+28
| | | | | | In addition to the non-monolithic variant. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add support for monolithic ES-GSMarek Olšák2017-04-282-9/+72
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: make sure the 1st shader's main part exists for merged shadersMarek Olšák2017-04-281-18/+60
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: select shader parts for non-monolithic ES-GSMarek Olšák2017-04-281-3/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add GS prolog support for merged ES-GSMarek Olšák2017-04-281-17/+70
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add VS prolog support for merged ES-GSMarek Olšák2017-04-281-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GSMarek Olšák2017-04-281-0/+32
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: store ES outputs to LDSMarek Olšák2017-04-281-4/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: load GS inputs from LDSMarek Olšák2017-04-281-6/+39
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: get GS wave ID from the correct inputMarek Olšák2017-04-281-3/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add the function signature of merged ES-GSMarek Olšák2017-04-282-12/+74
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set registers and shader key for merged ES-GSMarek Olšák2017-04-285-27/+218
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add GS user SGPRsMarek Olšák2017-04-284-7/+25
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename declare_tess_lds -> declare_lds_as_pointerMarek Olšák2017-04-281-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: simplify some shader type conditionsMarek Olšák2017-04-281-6/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename the swizzle parameter of lds_storeMarek Olšák2017-04-281-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add si_shader::prolog2Marek Olšák2017-04-283-1/+25
| | | | | | For a GS prolog in merged ES-GS. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shadersMarek Olšák2017-04-283-21/+24
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add support for monolithic merged LS-HSMarek Olšák2017-04-282-17/+128
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between themMarek Olšák2017-04-281-2/+41
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't store the HS control wordMarek Olšák2017-04-281-7/+12
| | | | | | GFX9 doesn't have it. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: pass inputs from LS to TCSMarek Olšák2017-04-282-2/+69
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add TCS epilog support for merged LS-HSMarek Olšák2017-04-281-34/+76
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add VS prolog support for merged LS-HSMarek Olšák2017-04-282-10/+21
| | | | | | HS input VGPRs must be reserved. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: merged shaders have scratch offset at the beginningMarek Olšák2017-04-282-1/+13
| | | | | | also, screen wasn't initialized for compute shaders Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: define LS-HS main shader function prototypeMarek Olšák2017-04-281-38/+147
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamicallyMarek Olšák2017-04-283-193/+190
| | | | | | They will vary with merged stages. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: define and set LS-HS user SGPRsMarek Olšák2017-04-285-20/+57
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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