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* gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-0617-0/+18
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: scan address operands (v2)Marek Olšák2017-10-061-1/+42
| | | | | | v2: set swizzled usage mask Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: set correct usage mask for tex offsets in scan_src_operandMarek Olšák2017-10-061-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: take advantage of already swizzled usage mask in scan_src_operandMarek Olšák2017-10-061-30/+17
| | | | | | It has always been a usage mask *after* swizzling. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: set non-valid src_index for tex offsets in scan_src_operandMarek Olšák2017-10-061-1/+1
| | | | | | tex offsets are not "Src" operands. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: implement tgsi_util_get_inst_usage_mask properlyMarek Olšák2017-10-063-124/+206
| | | | | | All opcodes are handled. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: add docs for some existing pack opcodesMarek Olšák2017-10-061-3/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Enable VK_KHR_maintenance2 extension.Bas Nieuwenhuizen2017-10-062-0/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make tess winding order a bit more intuitive.Bas Nieuwenhuizen2017-10-061-3/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Allow setting the domain origin in tess.Bas Nieuwenhuizen2017-10-061-1/+9
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Disable usage checks in metadata for images with extended usage data.Bas Nieuwenhuizen2017-10-061-1/+3
| | | | | | | The app can extend the usage, so knowing that the usage is limitied does not help us here. Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement querying the point clipping behavior.Bas Nieuwenhuizen2017-10-061-0/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* broadcom: Fix out-of-tree build include pathDaniel Stone2017-10-052-1/+5
| | | | | Reviewed-by: Eric Anholt <[email protected]> Fixes: 5b102160ae ("broadcom/genxml: Introduce a V3D packet/struct decoder.")
* meson: generate builddir/src/amd/vulkan/dev_icd.jsonBas Nieuwenhuizen2017-10-053-2/+9
| | | | Reviewed-by: Dylan Baker <[email protected]>
* mesa: Use a 565 format for GL_RGB and GL_UNSIGNED_SHORT_5_6_5 textures.Kenneth Graunke2017-10-051-0/+3
| | | | | | | | | | Found while trying to optimize an application. Not observed to help performance on i965, but should at least reduce the memory usage of such textures a bit. Reviewed-by: Eric Anholt <[email protected]> Tested-by: Eero Tamminen <[email protected]>
* intel/compiler: Don't propagate cmod into integer multipliesJason Ekstrand2017-10-052-0/+34
| | | | | | | No shader-db change on Sky Lake. Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
* intel/compiler: Don't cmod propagate into a saturated operationJason Ekstrand2017-10-052-0/+16
| | | | | | | | | | | | Shader-db results on Sky Lake: total instructions in shared programs: 12954445 -> 12955125 (0.01%) instructions in affected programs: 141862 -> 142542 (0.48%) helped: 0 HURT: 626 Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
* broadcom/vc4: Don't advertise tiled dmabuf modifiers if we can't use themDerek Foreman2017-10-051-13/+18
| | | | | | | | | | | | | | | | If the DRM_VC4_GET_TILING ioctl isn't present then we can't tell if a dmabuf bo is tiled or linear, so will always assume it's linear. By not advertising tiled formats in this situation we ensure the assumption is correct. This fixes a bug where most attempts to render a gl wayland client under weston will result in a client side abort. Signed-off-by: Derek Foreman <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Daniel Stone <[email protected]> (on irc)
* egl: Simplify the "driver" interfaceAdam Jackson2017-10-055-262/+22
| | | | | | | | | | | | | | | | | | "Driver" isn't a great word for what this layer is, it's effectively a build-time choice about what OS you're targeting. Despite that both of the extant backends totally ignore the display argument, the old code would only set up the backend relative to a display. That causes problems! One problem is it means eglGetProcAddress can generate X or Wayland protocol when it tries to connect to a default display so it can call into the backend, which is, you know, completely bonkers. Any other EGL API that doesn't reference a display, like EGL_EXT_device_query, would have the same issue. Fortunately this is a problem that can be solved with the delete key. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* loader/dri3: Don't accidently free buffer holding new back contentThomas Hellstrom2017-10-051-7/+9
| | | | | | | | | | | Avoid freeing buffers holding new back content (with GLX_SWAP_COPY_OML and GLX_SWAP_EXCHANGE_OML) Prevously that would have resulted in back buffer content becoming incorrect after a swap, although I haven't managed to trigger such a situation yet. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
* loader/dri3: Avoid resizing existing buffers in dri3_find_back_allocThomas Hellstrom2017-10-051-10/+31
| | | | | | | | Resize only in loader_dri3_get_buffers(), where the dri driver has a chance to immediately update the viewport. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
* loader/dri3: Use local blits and local buffers when resizingThomas Hellstrom2017-10-051-26/+24
| | | | | | | | | When a drawable is resized, and we fill the resized buffers, with data from the old buffers, use a local blit if there is a local buffer (back or fake front), and we have local blitting capability. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
* gallivm/ppc64le: allow environmental control of Altivec code generationBen Crocker2017-10-051-8/+24
| | | | | | | | | | | | | | In check_os_altivec_support(), allow control of Altivec (first PPC vector instruction set) code generation via a new environmental control, GALLIVM_ALTIVEC, which is expected to take on a value of 1 or 0. The default is to enable Altivec code generation. This environmental control of Altivec code generation is initially available only #ifdef DEBUG. Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* gallivm/ppc64le: adjust VSX code generation control.Ben Crocker2017-10-051-7/+30
| | | | | | | | | | | | | | | | | | | | | | | In lp_build_create_jit_compiler_for_module(), advance the minimum version of LLVM for VSX code generation to 4.0; this is the minimum revision at which several known VSX code generation bugs are fixed: https://llvm.org/bugs/show_bug.cgi?id=25503 (fixed in 3.8.1) https://llvm.org/bugs/show_bug.cgi?id=26775 (fixed in 3.8.1) https://llvm.org/bugs/show_bug.cgi?id=33531 (fixed in 4.0) An llc performance bug introduced in LLVM 4.0, https://llvm.org/bugs/show_bug.cgi?id=34647 is still pending as of LLVM 5.0, but only has a pronounced effect on one of the Piglit tests: ext_transform_feedback-max-varyings. All changes tested via Piglit. Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* gallivm: allow additional llc optionsBen Crocker2017-10-051-0/+23
| | | | | | | | | | | | | | | | In init_native_targets, allow the passing of additional options to the LLC compiler via new GALLIVM_LLC_OPTIONS environmental control. This option is available only #ifdef DEBUG, initially. At top, add #include <llvm-c/Support.h> for LLVMParseCommandLineOptions() declaration. v2: Fix compile error with old llvm versions (sroland) Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix typo in debug_printf messageBen Crocker2017-10-051-1/+1
| | | | | | | | | | In gallivm_compile_module, fix a typo in the debug_printf("Invoke as \"llc ..." message. Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radv: remove useless checks around radv_CmdBindPipeline()Samuel Pitoiset2017-10-048-97/+34
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check that pipeline is different before binding itSamuel Pitoiset2017-10-041-2/+8
| | | | | | | | We only need to dirty the descriptors when the pipeline is a new one, because user SGPRs can be potentially different. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Validate "Special Requirements for Handling Double Precision Data Types"Matt Turner2017-10-042-0/+792
| | | | | | | | | | | | | I did not implement: CNL's restriction on 64-bit int + align16, because I don't think we'll ever use this combination regardless of hardware generation. The restriction on immediate DF -> F conversions, because there's no reason to ever generate that, and I don't even know how DF -> F conversions are supposed to work in Align16 since (1) the dst stride must be 1, but (2) the dst stride would have to be 2 for src and dst strides to be aligned.
* i965: Fix and enable forgotten validation testMatt Turner2017-10-041-14/+17
| | | | I seem to have forgotten I still had work to do.
* i965: Only insert error message if not already presentMatt Turner2017-10-041-5/+13
| | | | | | | Some restrictions require something like strides to match between src and dest. For multi-source instructions, I'd rather encapsulate the logic for not inserting already present errors in ERROR_IF than open-coding it multiple places.
* i965: Avoid validation error when src1 is not presentMatt Turner2017-10-041-1/+1
| | | | | There can be no violation of the restriction that source offsets are aligned if there is only one source offset.
* i965: Remove validate_reg()Matt Turner2017-10-041-80/+0
| | | | | Replaced by the assembly validator, and in fact gets in the way of writing tests for the assembly validator.
* i965: Add and use STRIDE and WIDTH macrosMatt Turner2017-10-041-18/+15
| | | | | | You'll notice there were bugs in some of the code being replaced. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add parentheses around usage of macro argumentsMatt Turner2017-10-041-1/+1
| | | | | | Otherwise I cannot use this macro in test_eu_validate.cpp Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add GLK, CFL, CNL to test_eu_validate.cMatt Turner2017-10-041-0/+7
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* i965: Add Atom graphics names to parse_devid_override()Matt Turner2017-10-041-0/+3
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* i965: Fix support for disassembling 64-bit integer immediatesMatt Turner2017-10-041-2/+2
| | | | | | | The type suffixes were wrong, and the 16 was missing the 0 prefix. Fixes: 92f787ff86ab ("i965: Add support for disassembling 64-bit integer immediates") Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | ... without the float -> double conversion. Low power parts have additional restrictions when it comes to operating on 64-bit types, and the instruction used to do the conversion violates one of them: specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword". Previously we generated a float and then converted, but we can avoid the conversion by using the same extract-the-sign-bit + or-in-1.0 algorithm by directly operating on the high four bytes of each double-precision component in the result. In SIMD8 and SIMD16 this cuts one instruction from the implementation, and more importantly that instruction is the one which violated the regioning restriction. Along the way I removed some comments that I did not think helped, and some code about double comparisons which does not seem to be necessary today. This prevents validation failures caught by the new EU validation code added in later patches. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | 64-bit operations on Atom parts have additional restrictions over their big-core counterparts (validated by later patches). Specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword" is violated by most shift operations since NIR uses a 32-bit value as the shift count argument, and this causes instructions like shl(8) g19<1>Q g5<4,4,1>Q g23<4,4,1>UD where src1 has a 32-bit stride, but the dest and src0 have a 64-bit stride. This caused ~4 pixels in the ARB_shader_ballot piglit test fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no ARB_gpu_shader_int64 test hit this case because they operate on uniforms, and their scalar regions are an exception to the restriction. We work around this by effectively unpacking the shift count, so that we can read it with a 64-bit stride in the shift instruction. Unfortunately the unpack (a MOV with a dst stride of 2) is a partial write, and cannot be copy-propagated or CSE'd. Bugzilla: https://bugs.freedesktop.org/101984
* i965/fs: Don't apply POW/FDIV workaround on Gen10+Matt Turner2017-10-041-0/+1
| | | | | | The documentation says it applies only to Gens 8 and 9. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Fix src0 vs src1 typoMatt Turner2017-10-041-1/+1
| | | | | | | | | | | | | | | | A typo caused us to copy src0's reg file to src1 rather than reading src1's as intended. This caused us to fail to compact instructions like mov(8) g4<1>D 0D { align1 1Q }; because src1 was set to immediate rather than architecture file. Fixing this reenables compaction (after the precompact() pass changes the data types): mov(8) g4<1>UD 0x00000000UD { align1 1Q compacted }; Fixes: 1cb0a7941b27 ("i965: Switch to using the logical register types") Reviewed-by: Kenneth Graunke <[email protected]>
* radv: enable tc compatible htile for d32s8 also.Dave Airlie2017-10-041-1/+2
| | | | | | | | | | | | This enables tc compatible htile for stencil surfaces as well. This gives a 3-5fps boost on Mad Max on high@4k. It also depends on Bas's tc-compat htile patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: dump SPIRV when a GPU hang is detectedSamuel Pitoiset2017-10-044-4/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: dump NIR when a GPU hang is detectedSamuel Pitoiset2017-10-044-11/+27
| | | | | | | | This looks a bit ugly to me, but the existing codepath is not terribly elegant as well. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: silence a warningMarek Olšák2017-10-041-1/+3
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* egl/wayland: Don't use dmabuf with no modifiersDaniel Stone2017-10-041-7/+11
| | | | | | | | | | | | | | | | | The dmabuf interface requires a valid modifier to be sent. If we don't explicitly get a modifier from the driver, we can't know what to send; it must be inferred from legacy side-channels (or assumed to linear, if none exists). If we have no modifier, then we can only have a single-plane format anyway, so fall back to the old wl_drm buffer import path. Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them") Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers") Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Andy Furniss <[email protected]> Cc: Marek Olšák <[email protected]>
* egl/wayland: Check queryImage return for wl_bufferDaniel Stone2017-10-041-15/+41
| | | | | | | | | | | | | | | When creating a wl_buffer from a DRIImage, we extract all the DRIImage information via queryImage. Check whether or not it actually succeeds, either bailing out if the query was critical, or providing sensible fallbacks for information which was not available in older DRIImage versions. Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them") Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers") Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Andy Furniss <[email protected]> Cc: Marek Olšák <[email protected]>
* travis: move include path from $CC to $CFLAGSEric Engestrom2017-10-041-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* wayland-egl: adds CFLAGS for wayland.egl.h includeTobias Klausmann2017-10-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with commit ab0589c6ed ("wayland-egl: remove no longer needed wayland-client dependency") the wayland-egl.h include was missing leading to a build failure: CC wayland-egl.lo wayland-egl.c:33:10: fatal error: wayland-egl.h: No such file or directory #include "wayland-egl.h" ^~~~~~~~~~~~~~~ Strictly speaking we should be checking for wayland-egl in configure and propagating its CFLAGS here. Yet again, the current wayland-egl split is bonkers as the Wayland repo provides single header, no pkg-config file or library. That will be resolved at a later stage, but in the meanwhile fix the build. Fixes: ab0589c6ed ("wayland-egl: remove no longer needed wayland-client dependency") Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Emil Velikov <[email protected]> [Emil Velikov: add some text about CFLAGS and current wayland-egl situation] Signed-off-by: Emil Velikov <[email protected]>
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