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* Revert "radv/gfx9: fix block compression texture views."Bas Nieuwenhuizen2017-12-291-35/+0
| | | | | | | | | This reverts commit 59515780433837ad3975f8ed20b93cf2fe6870e5. The mentioned commit causes a hang in DoW3 on Vega. Fixes: 59515780433 "radv/gfx9: fix block compression texture views." Acked-by: Dave Airlie <[email protected]>
* svga: update SVGA_NEW_ flags for updating sampler stateBrian Paul2017-12-281-3/+4
| | | | | | | | | | | The SVGA_NEW_FS flag is needed since we now examine the fragment shader's fs_shadow_compare_units flags. The SVGA_NEW_TEXTURE_FLAGS flag is not needed since it's only for pre-VGPU10. No piglit changes. This doesn't fix any known issues but it could pop up somewhere. Suggested by Charmaine. Reviewed-by: Charmaine Lee <[email protected]>
* svga: whitespace, formatting fixes in svga_state_tss.cBrian Paul2017-12-281-34/+21
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* radv/gfx9: use correct swizzle parameter to work out border swizzle.Dave Airlie2017-12-291-2/+2
| | | | | | | | | | This should fix: dEQP-VK.pipeline.sampler.view_type.*.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black and a few others in that area. Fixes: b11c4a5546 (radv: add texture descriptor/fmask/cmask support for GFX9) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use a bigger hammer to flush cb/db caches.Dave Airlie2017-12-291-1/+8
| | | | | | | | | | | | amdvlk is probably more subtle than this but it never uses the inv cb/db variants, we fail some CTS tests without this. Fixes: dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> (for now :-) Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix block compression texture views.Dave Airlie2017-12-291-0/+35
| | | | | | | | | | | | This ports a fix from amdvlk, to fix the sizing for mip levels when block compressed images are viewed using uncompressed views. Fixes: dEQP-VK.image.texel_view_compatible.graphic.extended*bc* Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix buffer to image for 3d images on compute queuesDave Airlie2017-12-292-15/+48
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix 3d image clears on compute queuesDave Airlie2017-12-292-9/+65
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix 3d image to image transfers on compute queues.Dave Airlie2017-12-292-20/+56
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv/device: Mark all state buffers as needing captureJason Ekstrand2017-12-281-3/+3
| | | | | | | Previously, we were flagging the instruction state buffer for capture but not surface state or dynamic state. We want those captured too. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/aubinator: Gracefully handle dynamic state not being availableJason Ekstrand2017-12-281-0/+5
| | | | | | | | Some older versions of the Vulkan driver didn't properly tag dynamic state as needing to be captured. Also, this prevents crashes when looking at dumps on older kernels. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/aubinator: Free section data lastJason Ekstrand2017-12-281-2/+4
| | | | | | | | | We were walking the sections, printing the batches, and then freeing them in one pass. If the batch happens to reference any earlier sections (which it almost certainly will since it's at the end), we will access freed memory. Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: consider bitsize when handling OpSwitch casesEero Tamminen2017-12-281-3/+11
| | | | | | | | | | | | This reverts commit 7665383a33f9ce9256aa121cbe4d3bd948dff145 and is squashed together with https://patchwork.freedesktop.org/patch/194610/ (spirv: avoid infinite loop / freeze in vtn_cfg_walk_blocks()) which fixes https://bugs.freedesktop.org/show_bug.cgi?id=104359 properly. Fixes: 9702fac68e (spirv: consider bitsize when handling OpSwitch cases) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104359 Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* svga: check for null fs pointer in update_samplers()Brian Paul2017-12-281-1/+1
| | | | | | | | This can happen when there's no active fragment shader, such as when using transform feedback. This wasn't hit by any Piglit test but is hit by Daniel Rákos' Nature demo. VMware bug 2026189. Reviewed-by: Charmaine Lee <[email protected]>
* st/mesa: increase size of glsl_base_type bitfieldsBrian Paul2017-12-282-3/+4
| | | | | | | | | Change 59f458cd8703b97b31b8 added more enums to glsl_base_type. We have to bump up the size of the bitfields for fields of this type for MSVC. Also, add another assertion to catch another place where this enum bitfield is used. Reviewed-by: Neha Bhende <[email protected]>
* radv: fix pipeline statistics end query on compute queueDave Airlie2017-12-281-1/+1
| | | | | | | | | | | | It's legal to a pipeline stat query on a compute queue, but we'd emit the wrong packet here. This should fix it to emit the correct packet. Noticed while inspecting the mpv hang. Fixes: ad61eac250 (radv: factor out eop event writing code. (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix events on compute queues.Dave Airlie2017-12-281-1/+1
| | | | | | | | | | | The event emission wasn't sending the correct packet for gfx8 compute queues, which explains why it works on vega fine. This fixes the mpv vulkan hang. Fixes: ad61eac250 (radv: factor out eop event writing code. (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move local bos usage to a perftest flag.Dave Airlie2017-12-285-1/+5
| | | | | | | | | | These seem mildly unstable on vega, crashing CTS in various fun ways, and looks like leaking memory. Disable for now, but leave the option to enable them. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vulkan/wsi: free cmd poolsDave Airlie2017-12-281-0/+1
| | | | | | | | | | | We destroy the pools but don't free the container. This fixes: dEQP-VK.wsi.xlib.swapchain.simulate_oom* Fixes: d50937f137 (vulkan/wsi: Implement prime in a completely generic way) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Always use fragment resolve if dest uses DCC.Bas Nieuwenhuizen2017-12-281-5/+4
| | | | | | | HW resolve does not support it either. Fixes: 2a04f5481df "radv/meta: select resolve paths" Reviewed-by: Dave Airlie <[email protected]>
* radv: Use correct framebuffer size for partial FS resolves.Bas Nieuwenhuizen2017-12-281-2/+2
| | | | | | | Framebuffer is from 0,0, not (dst.x, dst.y). Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix fragment resolve destination offset.Bas Nieuwenhuizen2017-12-281-2/+2
| | | | | | | | | | The position start at (dst.x, dst.y), so if we want the source to start at (src.x, src.y), we have to offset by (src.x-dst.x,src.y-dst.y). Haven't tested that this fixed anything yet, but found by inspection. Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't handle DCC in compute resolve.Bas Nieuwenhuizen2017-12-281-4/+1
| | | | | | If the destination has DCC, we will use the FS resolve. Reviewed-by: Dave Airlie <[email protected]>
* radv: Flush caches before subpass resolve.Bas Nieuwenhuizen2017-12-282-0/+18
| | | | | Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* radv: Invert condition for all samples identical during resolve.Bas Nieuwenhuizen2017-12-281-1/+1
| | | | | | | | the samples_identical instruction returns 0 if they are differet, so we have to do the extra work if the result is 0, not if it is != 0. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* egl: don't try the software path twiceEric Engestrom2017-12-271-1/+1
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Brendan King <[email protected]>
* egl: rename LIBGL_ALWAYS_SOFTWARE variable from UseFallback to ForceSoftwareEric Engestrom2017-12-277-8/+8
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWAREEric Engestrom2017-12-273-4/+8
| | | | | | | | | | | | | | | | My refactor in 47273d7312cb5b5b6b0b9 missed this early return; because of it, setting UseFallback one layer above actually prevented the software path from being used. Remove this early return and let each platform's dri2_initialize_*() decide what it can do with the LIBGL_ALWAYS_SOFTWARE restriction. platform_{surfaceless,x11,wayland} were already handling it themselves. Fixes: 47273d7312cb5b5b6b0b9 "egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Brendan King <[email protected]>
* egl: link libEGL against the dynamic version of libglapiBrendan King2017-12-271-3/+6
| | | | | | | | | | | | | | | | | | | | | | Note: the following happens only when using slibtool. Since this is a very serious breakage, we will keep the workaround until a better solution is available. DRI modules store the address of the dispatch table in a TLS variable, _glapi_tls_Dispatch. Changes to the way libEGL is built in d884d8d0077c16d459b1 resulted in it being statically linked against libglapi, and thus containing its own copy of _glapi_tls_Dispatch. The result was that some applications would fail to work (e.g. deqp-egl, which dynamically loads libEGL), due to the DRI module storing the dispatch table address in one copy of _glapi_tls_Dispatch, and libEGL obtaining the address from another copy of the variable. Fixes: d884d8d0077c16d459b1 "egl/dri: link directly to libglapi.so" Signed-off-by: Brendan King <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radv: don't do format replacement on tc compat htile surfaces.Dave Airlie2017-12-281-1/+2
| | | | | | | | | | | | For copies the texture unit needs to know the depth format so it can read the htile data properly. This fixes: dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use correct stencil format for tc compat htile.Dave Airlie2017-12-281-4/+7
| | | | | | | | | | | This needs to correspond to the bit depth of the Z plane. noticed in passing reading amdvlk. Fixes: fc6c77e162df3 (radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: move variant->fs_shadow_compare_units assignmentBrian Paul2017-12-271-2/+2
| | | | | | | Fixes a crash since the variant object isn't allocated until later in the function. Not sure how this got through. Reviewed-by: Charmaine Lee <[email protected]>
* amd/common: rework set_userdata_location() and rename to set_loc()Samuel Pitoiset2017-12-271-8/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename set_userdata_location_shader() to set_loc_shader()Samuel Pitoiset2017-12-271-27/+30
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace set_userdata_location_indirect() by set_loc_desc()Samuel Pitoiset2017-12-271-11/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_vs_user_sgprs_phase2()Samuel Pitoiset2017-12-271-22/+33
| | | | | | | ... to set_vs_specific_input_locs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_common_user_sgprs_phase2()Samuel Pitoiset2017-12-271-43/+50
| | | | | | | ... to set_global_input_locs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename add_user_sgpr_array_argument() to add_array_arg()Samuel Pitoiset2017-12-271-9/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_sgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-45/+33
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_user_sgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-45/+58
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_vgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-51/+60
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add new add_arg() helper for SGPRs/VGPRs argumentsSamuel Pitoiset2017-12-271-0/+24
| | | | | | | The idea is to clean up the add arguments logic. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_common_user_sgprs_phase1()Samuel Pitoiset2017-12-271-38/+74
| | | | | | | ... to declare_global_input_sgprs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_vs_user_sgprs_phase1()Samuel Pitoiset2017-12-271-21/+42
| | | | | | | ... to declare_vs_specific_inputs_sgprs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: do not try to declare input VS SGPRs for GSSamuel Pitoiset2017-12-271-1/+0
| | | | | | | It's a no-op anyway but it looked strange to me, remove it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add declare_vs_input_vgprs() helperSamuel Pitoiset2017-12-271-14/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add declare_tes_input_vgprs() helperSamuel Pitoiset2017-12-271-8/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: remove unnecessary num_user_sgprs_usedSamuel Pitoiset2017-12-271-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: remove unnecessary user_sgpr_countSamuel Pitoiset2017-12-271-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: make use of ac_init_exec_full_mask()Samuel Pitoiset2017-12-271-11/+3
| | | | | | | Similar to si_init_exec_full_mask(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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