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* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-192-3/+3
* intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_valuesJason Ekstrand2018-11-194-34/+50
* gbm: add missing comma between stringsEric Engestrom2018-11-191-1/+1
* radv: implement fast HTILE clears for depth or stencil only on GFX9Samuel Pitoiset2018-11-192-5/+269
* radv: rewrite the condition that checks allowed depth/stencil valuesSamuel Pitoiset2018-11-191-8/+4
* radv: check allowed fast HTILE clears a bit earlierSamuel Pitoiset2018-11-191-0/+5
* radv: add radv_is_fast_clear_{depth,stencil}_allowed() helpersSamuel Pitoiset2018-11-191-2/+16
* radv: add radv_get_htile_fast_clear_value() helperSamuel Pitoiset2018-11-191-3/+18
* radv: remove unnecessary goto in the fast clear pathsSamuel Pitoiset2018-11-191-28/+24
* radv/winsys: remove the max IBs per submit limit for the sysmem pathSamuel Pitoiset2018-11-191-17/+29
* radv/winsys: remove the max IBs per submit limit for the fallback pathSamuel Pitoiset2018-11-191-48/+55
* etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach2018-11-193-2/+19
* virgl: fix vtest regression since fencing changes.Dave Airlie2018-11-191-0/+1
* radv: always clear the FCE predicate after DCC/FMASK/CMASK decompressionsSamuel Pitoiset2018-11-191-5/+8
* radv: tidy up radv_set_dcc_need_cmask_elim_pred()Samuel Pitoiset2018-11-195-15/+14
* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
* i965:use FRAMEBUFFER_UNSUPPORTED instead of FRAMEBUFFER_INCOMPLETE_DIMENSIONSGert Wollny2018-11-191-1/+1
* virgl: Use file descriptor instead of un-allocated objectGert Wollny2018-11-191-1/+1
* i965: Add support for and expose EXT_texture_sRGB_R8Gert Wollny2018-11-192-0/+2
* i965: Force zero swizzles for unused components in GL_RED and GL_RGGert Wollny2018-11-191-0/+4
* i965: be more specific about FBO completeness errorsGert Wollny2018-11-191-19/+23
* i965: Correct L8_UNORM_SRGB table entryGert Wollny2018-11-191-1/+1
* virgl: Clean up fences commitRobert Foss2018-11-184-4/+1
* i915: Delete swizzling detection logic.Kenneth Graunke2018-11-174-31/+0
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-164-16/+26
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin2018-11-161-1/+1
* egl: Print the actual message to the console from _eglError().Eric Anholt2018-11-161-12/+20
* loader: Factor out the common driver opening logic from each loader.Eric Anholt2018-11-1615-238/+131
* loader: Stop using a local definition for an in-tree headerEric Anholt2018-11-161-8/+2
* egl: Move loader_set_logger() up to egl_dri2.c.Eric Anholt2018-11-165-10/+2
* glx: Move DRI extensions pointer loading to driOpenDriver().Eric Anholt2018-11-166-52/+26
* glx: Remove an old DEFAULT_DRIVER_DIR default.Eric Anholt2018-11-162-6/+2
* radv: enable primitive binning by defaultSamuel Pitoiset2018-11-162-7/+3
* radv: add a debug option for disabling primitive binningSamuel Pitoiset2018-11-162-0/+2
* virgl: native fence fd supportRobert Foss2018-11-167-16/+166
* intel/aub_viewer: Print blend states properlyLionel Landwerlin2018-11-161-2/+16
* intel/aub_viewer: fix dynamic state printingLionel Landwerlin2018-11-161-2/+2
* intel/aubinator: fix ring buffer pointerLionel Landwerlin2018-11-162-4/+4
* intel/decoders: read ring buffer lengthLionel Landwerlin2018-11-162-2/+5
* egl/dri: fix error value with unknown drm formatLionel Landwerlin2018-11-161-1/+1
* gbm: Clarify acceptable formats for gbm_boDaniel Stone2018-11-161-2/+2
* Revert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT"Connor Abbott2018-11-161-4/+2
* vc4: Don't return a vc4 BO handle on a renderonly screen.Eric Anholt2018-11-151-2/+4
* vc4: Make sure we make ro scanout resources for create_with_modifiers.Eric Anholt2018-11-151-1/+9
* i965: Fix calculation of layers array length for isl_viewDanylo Piliaiev2018-11-151-15/+18
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-157-405/+421
* nir: Add alignment parameters to SSBO, UBO, and shared accessJason Ekstrand2018-11-157-10/+85
* nir/lower_io: Add shared to get_io_offset_srcJason Ekstrand2018-11-151-0/+2
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