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* radeonsi: add support for displayable DCC for 1 RB chipsMarek Olšák2019-04-047-7/+113
| | | | This is the simpler codepath - just disable RB and pipe alignment for DCC.
* radeonsi: add ability to bind images as image buffersMarek Olšák2019-04-042-3/+8
| | | | so that we can bind DCC (texture) as an image buffer.
* radeonsi/gfx9: add support for PIPE_ALIGNED=0Marek Olšák2019-04-044-12/+30
| | | | | | Needed by displayable DCC. We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
* amd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoordMarek Olšák2019-04-041-0/+2
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: move variable to the scope where it is being usedTapani Pälli2019-04-041-1/+1
| | | | | | | | | iris_upload_border_color is passed a pointer which points to variable that is introduced in a different scope. CID: 1444296 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/nir: run st_nir_opts after 64bit ops loweringTapani Pälli2019-04-041-1/+1
| | | | | | | | CID: 1444309 Fixes: 9ab1b1d0227 "st/nir: Move 64-bit lowering later" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* panfrost: Size tiled temp buffers correctlyAlyssa Rosenzweig2019-04-043-8/+13
| | | | | | | | This should lower transient memory usage and improve performance slightly (due to less memory to malloc/free, better cache locality, etc). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect box->width in tiled storesAlyssa Rosenzweig2019-04-043-4/+6
| | | | | | | This fixes a regression uploading partial tiled textures introduced sometime during the cubemap series. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Cleanup some indirection in pan_resourceAlyssa Rosenzweig2019-04-041-24/+21
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement system valuesAlyssa Rosenzweig2019-04-047-188/+229
| | | | | | | | | | | | | | | | | | This patch implements system values via specially-crafted uniforms. While we previously had an ad hoc system for passing the viewport into the vertex shader, this commit generalizes the system to allow for arbitrary system values to be added to both shader stages. While we're at it, we clean up uniform handling code (which was considerably muddied to handle the ad hoc viewport uniform). This commit serves as both a cleanup of the existing codebase and the precursor to new functionality, like implementing textureSize(). Concurrent with these changes is respecting the depth transform, which was not possible with the old fixed uniform system and here serves as a proof-of-correctness test (as well as justifying the NIR changes). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* nir: Add "viewport vector" system valuesAlyssa Rosenzweig2019-04-041-0/+5
| | | | | | | | | | | | While a partial set of viewport system values exist, these are scalar values, which is a poor fit for viewport transformations on vector ISAs like Midgard (where the vec3 values for scale and offset each need to be coherent in a vec4 uniform slot to take advantage of vectorized transform math). This patch adds vec3 scale/offset fields corresponding to the 3D Gallium viewport / glViewport+depth Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* virgl: also destroy all read-transfersErik Faye-Lund2019-04-032-2/+4
| | | | | | | | | | | | | | | For texture write-transfers, we either free them on the transfer-queue or right away. But for read-transfers, we currently only destroy them in case they used a temp-resource. This leads to occasional resource-leaks. Let's add a call to virgl_resource_destroy_transfer in the missing case. Do the same thing for buffers as well, but the logic is a bit easier to follow there. Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: f0e71b10888 ("virgl: use transfer queue") Reviewed-by: Gurchetan Singh <[email protected]>
* meson: Error if LLVM is turned off but clover it turned onDylan Baker2019-04-031-0/+2
| | | | | | | | Since clover has a hard requirement on LLVM v2: - make error message more specific Reviewed-by: Eric Engestrom <[email protected]>
* meson: Error if LLVM doesn't have rtti when building cloverDylan Baker2019-04-031-0/+2
| | | | We already do this for nouveau, but it's required for clover too.
* panfrost: Remove support for legacy kernelsAlyssa Rosenzweig2019-04-038-39/+8
| | | | | | | | | | | | | | Previously, there was minimal support for interoperating with legacy kernels (reusing kernel modules originally designed for proprietary legacy userspaces, rather than for upstream-friendly free software stacks). Now that the Panfrost kernel is stabilising, this commit drops the legacy code path. Panfrost users need to use a modern, mainline kernel supporting the Panfrost kernel driver from this commit forward. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* etnaviv: only try to construct scanout resource when on KMS winsysLucas Stach2019-04-031-1/+1
| | | | | | | | | | Trying to construct a scanout capable buffer will only ever work when when we are on top of a KMS winsys, as the render node isn't capable of allocating contiguous buffers. Tested-by: Marius Vlad <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: flush all pending contexts when accessing a resource with the CPULucas Stach2019-04-031-2/+8
| | | | | | | | | | | | | When setting up a transfer to a resource, all contexts where the resource is pending must be flushed. Otherwise a write transfer might be started in the current context before all contexts that access the resource in shared (read) mode have been executed. Fixes: 64813541d575 (etnaviv: fix resource usage tracking across different pipe_context's) Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-By: Guido Günther <[email protected]>
* etnaviv: don't flush own context when updating resource useLucas Stach2019-04-031-1/+10
| | | | | | | | | | | | The context is self synchronizing at the GPU side, as commands are executed in order. We must not flush our own context when updating the resource use, as that leads to excessive flushing on effectively every draw call, causing huge CPU overhead. Fixes: 64813541d575 (etnaviv: fix resource usage tracking across different pipe_context's) Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: shrink struct etna_3d_stateChristian Gmeiner2019-04-032-23/+0
| | | | | | | Drop struct members which are only written to but never read from. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* intel/compiler: use defined size for vector componentsDave Airlie2019-04-031-1/+1
| | | | | | | If we increase vector sizing later it would be nice to avoid tripped over this again. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: use proper array sizing define for vectorsDave Airlie2019-04-031-4/+4
| | | | | | | If we increase the vector size in the future it would be good to not have to fix these up, this should change nothing at present. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* Revert "nir: propagate known constant values into the if-then branch"Timothy Arceri2019-04-031-60/+0
| | | | | | This reverts commit 4218b6422cf1ff70c7f0feeec699a35e88522ed7. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311
* nir: propagate known constant values into the if-then branchTimothy Arceri2019-04-031-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Helps Max Waves / VGPR use in a bunch of Unigine Heaven shaders. shader-db results radeonsi (VEGA): Totals from affected shaders: SGPRS: 5505440 -> 5505872 (0.01 %) VGPRS: 3077520 -> 3077296 (-0.01 %) Spilled SGPRs: 39032 -> 39030 (-0.01 %) Spilled VGPRs: 16326 -> 16326 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 744 -> 744 (0.00 %) dwords per thread Code Size: 123755028 -> 123753316 (-0.00 %) bytes Compile Time: 2751028 -> 2560786 (-6.92 %) milliseconds LDS: 1415 -> 1415 (0.00 %) blocks Max Waves: 972192 -> 972240 (0.00 %) Wait states: 0 -> 0 (0.00 %) vkpipeline-db results RADV (VEGA): Totals from affected shaders: SGPRS: 160 -> 160 (0.00 %) VGPRS: 88 -> 88 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 18268 -> 18152 (-0.63 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 26 -> 26 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* virgl: close drm fd when destroying virgl screen.Lepton Wu2019-04-021-0/+1
| | | | | | | | This fd was create in virgl_drm_screen_create and should be closed in virgl_drm_screen_destroy. Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* iris: Enable fast clears on gen8.Rafael Antognolli2019-04-021-2/+1
| | | | | | | Since we are now properly storing the clear color with SCS bits, we can now enable fast clears on gen8 too. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add aux.sampler_usages.Rafael Antognolli2019-04-023-16/+34
| | | | | | | | | | | | | | We want to skip some types of aux usages (for instance, ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have multisampling) when sampling from the surface. Instead of checking for those cases while filling the surface state and leaving it blank, let's have a version of aux.possible_usages for sampling. This way we can also avoid allocating surface state for the cases we don't use. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Do not allocate clear_color_bo for gen8.Rafael Antognolli2019-04-022-6/+9
| | | | | | | | Since we are not using it for the clear color, there's no need to allocate it. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Manually apply fast clear color channel overrides.Rafael Antognolli2019-04-021-6/+16
| | | | | | | | | | | | At the fast clear time, the only swizzle we have available is actually the identity swizzle (which we use for most rendering). So the call to swizzle_color_value() becomes simply a no-op, and doesn't properly zero out the unused channels. We have to manually override those channels. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.Rafael Antognolli2019-04-021-10/+28
| | | | | | | | | | | | | | | | The swizzle for rendering surfaces is always identity. So when we are doing the fast clear, we don't have enough information to store the clear color OR'ed with the Shader Channel Select bits for the dword in the SURFACE_STATE. Instead of trying to patch up the SURFACE_STATE correctly later, by reading the color from the clear color state buffer and then doing all the operations to store it, let's just re-emit the whole SURFACE_STATE. That should make things way simpler on gen8, and we can still use the clear color state buffer for gen9+. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Only update clear color for gens 8 and 9.Rafael Antognolli2019-04-021-1/+10
| | | | | | | | | Newer gens can read it directly. Also properly skip updating the ISL_AUX_USAGE_NONE surface. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* haiku: Fix hgl dispatch build. Tested under meson/scons.Alexander von Gluck IV2019-04-021-1/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* docs: Fix 19.0.x version numbersGuido Günther2019-04-021-4/+4
| | | | | | | | The list has 19.0.2 twice. Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0Marek Olšák2019-04-022-2/+2
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* CI: use wayland ci-templates repo to create the base imageBenjamin Tissoires2019-04-023-182/+177
| | | | | | | | | | | | There shouldn't be a difference for users, but this way we do manage all of our containers from freedesktop.org note: compared to the provious Dockerfile, we need to manually add gcc, g++ and python*-wheel Signed-off-by: Benjamin Tissoires <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* radeonsi: don't use PFP_SYNC_ME with compute-only contextsMarek Olšák2019-04-021-1/+1
| | | | | | | | | | Compute rings don't have PFP. Fixes: a1378639ab1 "radeonsi: always use compute rings for clover on CI and newer (v2)" Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Jan Vesely <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* virgl: define MAX_VERTEX_STREAMS based on availability of TF3Gert Wollny2019-04-022-1/+3
| | | | | | | | | | Since with gles hosts we lie about the GLSL feature level it is better to set the number of streams based on actual hosts capabilities. v2: Make use of feature check level to avoid regressions. Signed-off-by: Gert Wollny <[email protected]> Reviewed-By: Reviewed-by: Gurchetan Singh <[email protected]>
* softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADDGert Wollny2019-04-022-10/+18
| | | | | | | | | | | | | | This enables the following piglits with PASS: nv_shader_atomic_float/execution/ shared-atomicadd-float shared-atomicexchange-float ssbo-atomicadd-float ssbo-atomicexchange-float v2: Minimize the patch by using type punning (Eric Anholt) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* virgl: stricter usage of compressed 3d texturesErik Faye-Lund2019-04-021-0/+6
| | | | | | | | | | | | | Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc, EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture, S3_s3tc or EXT_texture_compression_s3tc specifications. So let's not allow any of those compressed 3d-textures at all. It's not going to work once it hits the OpenGL driver in virglrenderer. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: do not allow compressed formats for buffersErik Faye-Lund2019-04-021-0/+3
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* dri3: Return the current swap interval from glXGetSwapIntervalMESA().Eric Anholt2019-04-012-3/+1
| | | | | | | | | We were caching only the value set with glXSwapIntervalSGI(), missing out on the default setting of the swap interval by the loader. This fixes glxgears's warning about being vblank synchronized by default. Fixes: 9777c4234b0e ("loader: drop the [gs]et_swap_interval callbacks") Reviewed-by: Ian Romanick <[email protected]>
* intel: Add support for Comet LakeAnuj Phogat2019-04-012-0/+19
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Adapt to variable ppGTT sizeChris Wilson2019-04-011-1/+20
| | | | | | | | | Not all hardware is made equal and some does not have the full complement of 48b of address space. Ask what the actual size of virtual address space allocated for contexts, and bail if that is not enough to satisfy our static partitioning needs. Reviewed-by: Kenneth Graunke <[email protected]>
* radv: partially enable VK_KHR_shader_float16_int8Samuel Pitoiset2019-04-013-0/+10
| | | | | | | Only 8-bit integers for now, float16 requires a bit more work. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()Samuel Pitoiset2019-04-011-0/+14
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 8-bit support to ac_build_umsb()Samuel Pitoiset2019-04-011-1/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 8-bit support to ac_find_lsb()Samuel Pitoiset2019-04-011-1/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 8-bit support to ac_build_bit_count()Samuel Pitoiset2019-04-011-0/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: add support for nir_op_b2i8Samuel Pitoiset2019-04-011-0/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: implement ARB/KHR_parallel_shader_compile callbacksMarek Olšák2019-04-011-0/+31
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* util/queue: add util_queue_adjust_num_threadsMarek Olšák2019-04-012-6/+52
| | | | | | for ARB_parallel_shader_compile Reviewed-by: Ian Romanick <[email protected]>
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