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* radv: Fix descriptor set allocation failure.Bas Nieuwenhuizen2019-07-301-1/+5
| | | | | | | | | | | | | | Set all the handles to VK_NULL_HANDLE: "If the creation of any of those descriptor sets fails, then the implementation must destroy all successfully created descriptor set objects from this command, set all entries of the pDescriptorSets array to VK_NULL_HANDLE and return the error." (Vulkan 1.1.117 Spec, section 13.2) CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: fix queries with WAIT_BIT returning VK_NOT_READYAndres Rodriguez2019-07-271-1/+1
| | | | | | | | | | | | | | | | | When vkGetQueryPoolResults() is called with VK_QUERY_RESULT_WAIT_BIT set, the driver is supposed to wait for the query to become available before returning. Currently, radv returns once the query is indeed ready, but it returns VK_NOT_READY. It also fails to populate the results. The problem is a missing volatile in the secondary check for query availability. This patch removes the secondary check altogether since it is redundant with the preceding loop. This bug was found with an unreleased version of SteamVR. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: Test for program_invocation_nameMatt Turner2019-07-303-7/+10
| | | | | | | | program_invocation_name and program_invocation_short_name are both GNU extensions. I don't believe one can exist without the other, so only check for program_invocation_name. Reviewed-by: Eric Engestrom <[email protected]>
* scons: Test for random_r()Matt Turner2019-07-301-0/+3
| | | | Suggested-by: Eric Engestrom <[email protected]>
* meson: Test for random_r()Matt Turner2019-07-302-2/+2
| | | | | | | It's better to test for needed functions instead of using external knowledge about presence in this or that C library. Reviewed-by: Eric Engestrom <[email protected]>
* st/nine: Drop preprocessor guards for glibc-2.12Matt Turner2019-07-301-3/+0
| | | | | | | | Same rationale as the previous patch, but additionally these checks just seem entirely unnecessary. pthread_self() has been used in Mesa since at least 1999. Acked-by: Eric Engestrom <[email protected]>
* util: Drop preprocessor guards for glibc-2.12Matt Turner2019-07-301-7/+0
| | | | | | | | glibc-2.12 was released in 2010. No one is building new Mesa against 9 year old glibc, and removing these checks allows the code to work on other C libraries like musl. Acked-by: Eric Engestrom <[email protected]>
* pan/midgard: Nothing to see here, move along folksAlyssa Rosenzweig2019-07-301-4/+4
| | | | | | Fixes: dee1e18fe4f ("pan/midgard: Cleanup ops table") Signed-off-by: Alyssa Rosenzweig <[email protected]>
* spirv: don't discard access set by vtn_pointer_dereferenceLionel Landwerlin2019-07-301-1/+1
| | | | | | | | | We can have a access flag already set here so just augment the existing ones. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 0fb61dfdeb ("spirv: propagate access qualifiers through ssa & pointer") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Enable EXT_texture_shadow_lodSagar Ghuge2019-07-301-0/+1
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: Add PIPE_CAP_TEXTURE_SHADOW_LODSagar Ghuge2019-07-304-0/+7
| | | | | | | | v2: Line wrap to 80 char (Marek Olsak) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable EXT_texture_shadow_lodSagar Ghuge2019-07-301-0/+1
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Add builtin functions for EXT_texture_shadow_lodPaulo Zanoni2019-07-301-0/+26
| | | | | | | | | | | | | With the help of Sagar, Ian and Ivan. v2: Fix dependencies (Ian Romanick) v3: 1) fix function name (Marek Olsak) 2) Add check for extension enable (Marek Olsak) Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Allow _textureCubeArrayShadow function to accept ir_texture_opcodePaulo Zanoni2019-07-301-4/+19
| | | | | | | | | | | This will be used to support one of the function from Ext_texture_shadow_lod specification. With the help of Sagar, Ian and Ivan. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: extension boilerplate for EXT_texture_shadow_lodPaulo Zanoni2019-07-304-0/+5
| | | | | | | | With the help of Sagar, Ian and Ivan. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* pan/midgard: Cleanup ops tableAlyssa Rosenzweig2019-07-301-7/+7
| | | | | | | Hopefully this should make a few ops make more sense. No functional changes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend copy-propagation to swizzlesAlyssa Rosenzweig2019-07-303-4/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can compose them when we rewrite, which is.. more code.. but helps. total instructions in shared programs: 3611 -> 3513 (-2.71%) instructions in affected programs: 672 -> 574 (-14.58%) helped: 11 HURT: 2 helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10 helped stats (rel) min: 5.71% max: 24.56% x̄: 17.99% x̃: 18.87% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 1.19% max: 2.08% x̄: 1.64% x̃: 1.64% 95% mean confidence interval for instructions value: -10.45 -4.62 95% mean confidence interval for instructions %-change: -20.07% -9.87% Instructions are helped. total bundles in shared programs: 2117 -> 2067 (-2.36%) bundles in affected programs: 356 -> 306 (-14.04%) helped: 11 HURT: 0 helped stats (abs) min: 1 max: 7 x̄: 4.55 x̃: 5 helped stats (rel) min: 4.55% max: 15.22% x̄: 13.63% x̃: 14.71% 95% mean confidence interval for bundles value: -5.64 -3.45 95% mean confidence interval for bundles %-change: -15.71% -11.55% Bundles are helped. total quadwords in shared programs: 3567 -> 3468 (-2.78%) quadwords in affected programs: 695 -> 596 (-14.24%) helped: 11 HURT: 1 helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10 helped stats (rel) min: 5.56% max: 21.88% x̄: 14.97% x̃: 15.15% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 2.38% max: 2.38% x̄: 2.38% x̃: 2.38% 95% mean confidence interval for quadwords value: -10.96 -5.54 95% mean confidence interval for quadwords %-change: -17.42% -9.63% Quadwords are helped. total registers in shared programs: 391 -> 383 (-2.05%) registers in affected programs: 46 -> 38 (-17.39%) helped: 9 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 10.00% max: 10.00% x̄: 10.00% x̃: 10.00% 95% mean confidence interval for registers value: -1.25 -0.35 95% mean confidence interval for registers %-change: -29.42% -13.58% Registers are helped. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extract simple source mod checkAlyssa Rosenzweig2019-07-303-4/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Lower texr/texw mixed registersAlyssa Rosenzweig2019-07-301-2/+2
| | | | | | | | | Conceptually, r28-r29 (as used for reading) and r28-r29 (as used for writing) aren't registers at all, merely push/pull arrangements. So you can't feed a texture result back into itself without explicitly moving in the middle. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Always set .cont for derivatives in loopsAlyssa Rosenzweig2019-07-301-0/+7
| | | | | | We need to keep the helper invocations alive. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement derivativesAlyssa Rosenzweig2019-07-305-1/+183
| | | | | | Implement the fdd* and fdd* opcodes in the Midgard compiler. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Compose original texture swizzle in RAAlyssa Rosenzweig2019-07-301-2/+4
| | | | | | Used for lowering derivatives. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add new swizzlesAlyssa Rosenzweig2019-07-301-0/+3
| | | | | | Used for derivatives. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add OP_IS_DERIVATIVE helperAlyssa Rosenzweig2019-07-301-0/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add make_compiler_temp_reg helperAlyssa Rosenzweig2019-07-301-0/+6
| | | | | | Corrollary to make_compiler_temp (for SSA). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Move nir_*_src_index to compiler.hAlyssa Rosenzweig2019-07-302-28/+30
| | | | | | These helpers are useful for code emission everywhere. Share the love! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Disassemble unknown texture ops as hexAlyssa Rosenzweig2019-07-301-1/+1
| | | | | | I'm not sure why I ever thought decimal was a good idea. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add support for disassembling derivativesAlyssa Rosenzweig2019-07-302-0/+12
| | | | | | They're just texture ops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* nir/find_array_copies: Use correct parent array lengthConnor Abbott2019-07-301-2/+3
| | | | | | | | | | | instr->type is the type of the array element, not the type of the array being dereferenced. Rather than fishing out the parent type, just use parent->num_children which should be the length plus 1. While we're here add another assert for the issue fixed by the previous commit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111251 Fixes: 156306e5e62 ("nir/find_array_copies: Handle wildcards and overlapping copies") Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Fix comparison for nir_deref_instr_is_known_out_of_bounds()Connor Abbott2019-07-301-1/+1
| | | | | | | | There was an off-by-one error. Fixes: 156306e5e62 ("nir/find_array_copies: Handle wildcards and overlapping copies") Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv/gfx10: only compile the GS copy shader on-demandSamuel Pitoiset2019-07-301-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gitlab-ci: Fix scons build directory pathMichel Dänzer2019-07-301-1/+1
| | | | | | Fixes: dd3d0b2897b8 "gitlab-ci: Only keep the build logs as artifacts." Reviewed-by: Eric Engestrom <[email protected]>
* swr/rasterizer: Add memory tracking supportJan Zielinski2019-07-3012-26/+252
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rasterizer: Better implementation of scatterJan Zielinski2019-07-307-79/+225
| | | | | | | | | | Added support for avx512 scatter instruction. Non-avx512 will now call into a C function to do the scatter emulation. This has better jit compile performance than the previous approach of jitting scalar loops. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rasterizer: cleanups for tessellationJan Zielinski2019-07-302-28/+56
| | | | | | | This commit introduces small fixes in preparation for tessellation support. Reviewed-by: Bruce Cherniak <[email protected]>
* rasterizer/swr: move BucketMgr to SwrContextJan Zielinski2019-07-3021-261/+290
| | | | | | | This move gets us back to parity with global manager in that we can dump render context buckets now. Reviewed-by: Bruce Cherniak <[email protected]>
* v3d: take into account separate_stencil when checking if stencil should be ↵Alejandro Piñeiro2019-07-301-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cleared In most cases this is not needed because the usual is that when a separate stencil is written, the parent resource is also written. This is needed if we have a separate stencil, no depth buffer, and the source and destination is the same, as in that case the stencil can be updated, but not the parent source (like if you are blitting only the stencil buffer). On that situation, the following access to the stencil buffer would clear the stencil buffer (so overwritting the previous blitting) cleared because the parent source has v3d_resource.writes to 0. As far as I see, that situation only happens with the GL_DEPTH32F_STENCIL8 format. Note that one alternative would consider that if the separate_stencil has been written, the parent should also be considered written (and update its "writes" field accordingly). But I found this patch more natural. Fixes the following piglit tests: spec/arb_depth_buffer_float/fbo-stencil-gl_depth32f_stencil8-blit spec/arb_depth_buffer_float/fbo-stencil-gl_depth32f_stencil8-copypixels the latter regressed when internally glCopyPixels implementation started to use blitting. So: Fixes: 131d40cfc91f ("st/mesa: accelerate glCopyPixels(STENCIL)") Reviewed-by: Eric Anholt <[email protected]>
* radv: Don't include radv_private.h from radv_shader.hDaniel Schürmann2019-07-306-94/+143
| | | | | | | This patch decouples radv_shader.h from any LLVM dependency. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965/gen10: Remove unnecessary workaround.Rafael Antognolli2019-07-291-16/+0
| | | | | | | | | | | | | | | | | | | | In fact, the description of the workaround states that the mask field doesn't work correctly on gen10, and we need to set it to 0xffff even we we only want to update a single field: "The mask bits are not implemented properly on 3DSTATE_3D_MODE. Driver must always program bits 31:16 of DW1 a value of 0xFFFF. This means if it is only updating 1 field, it must update all the fields to the correct value." So unless we want to change any of the fields of 3DSTATE_3D_MODE, there's not need to emit. Additionally, it seems this workaround is not required on gen11. And last but not least, this workaround is not implemented on iris or anv, and it doesn't seem to be missed there. So let's just remove the whole thing. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix SO offset to be 32-bit in DrawTransformFeedback handlingKenneth Graunke2019-07-291-1/+1
| | | | | | | | | | We accidentally started copying a full 64-bit value rather than copying a 32-bit offset and zeroing the top 32-bits. This caused us to compute bogus vertex counts which could lead to GPU hangs in some cases. Thanks to Clayton Craft for catching the regressions! Fixes: 0e24d10ff5c ("iris: Use gen_mi_builder to handle CS ALU operations.")
* intel: Use a system value for gl_FragCoordJason Ekstrand2019-07-2911-52/+19
| | | | | | | | | | | | It's kind-of an anomaly that the Intel drivers are still treating gl_FragCoord as an input. It also makes zero sense because we have to special-case it in the back-end. Because ANV is the only user of nir_lower_wpos_center, we go ahead and just update it to look for nir_intrinsic_load_frag_coord as part of this patch. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Treat gl_FragCoord as a varying even when it's a system valueJason Ekstrand2019-07-291-1/+3
| | | | | | | This fixes glsl-fcoord-invariant-pass.shader_test on drivers that set GLSLFragCoordIsSysVal which includes radeonsi among others. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/spirv: Set frag_coord_is_sysval to GLSLFragCoordIsSysValJason Ekstrand2019-07-291-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Remove calculate_urb_setup from fs_visitorJason Ekstrand2019-07-292-14/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/a6xx: fix MSAA resolve hangsRob Clark2019-07-291-11/+4
| | | | | | | | | Seems like RB_BLIT_SCISSOR needs to be aligned to (minimum?) tile size. Fixes intermittent GPU hangs triggered by some of the three.js samples on https://threejs.org/ Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix for array/reg store vs meta instructionsRob Clark2019-07-291-1/+4
| | | | | | | | | | | | | | | fishgl.com has a shader which does roughly: foo = texture(...); if (bar) foo = texture(...); after lowering phi webs to regs we end up w/ a vec4 reg (array). But since it was not an indirect access, we try to skip the extra mov. This results that the per-component fanout (split) meta instructions store directly to the reg (array). Which doesn't work out in RA. Signed-off-by: Rob Clark <[email protected]>
* meson: bump required version to 0.46Eric Engestrom2019-07-291-1/+1
| | | | | | | | | | | 0.45 has a few annoying bugs (like the one in !358 [1]), and 0.46 is well over a year old by now, so let's move to it. [1] https://gitlab.freedesktop.org/mesa/mesa/merge_requests/358 Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* radeon/vcn/vp9: add Arcturus VP9 supportLeo Liu2019-07-291-3/+3
| | | | | | | | Arcturus CHIP enum is less than Navi10, since it's still gfx9, but its VCN version belongs to VCN2.x Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/vcn: add Arcturus decode supportLeo Liu2019-07-291-1/+11
| | | | | | | different internal registers offset from previous HW Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* amd: add support for ArcturusMarek Olšák2019-07-294-0/+11
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
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