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* radeonsi: don't flush HTILE if there is no HTILE clearMarek Olšák2018-04-131-2/+2
* radeonsi: merge 2 identical if statements in si_clearMarek Olšák2018-04-131-9/+2
* radeonsi: don't do GFX-specific texture decompression for computeMarek Olšák2018-04-131-10/+10
* radeonsi: simplify generating the renderer stringMarek Olšák2018-04-131-11/+8
* winsys/amdgpu: allow local BOs on APUsMarek Olšák2018-04-131-1/+2
* getteximage: assume texture image is empty for non defined levelsJuan A. Suarez Romero2018-04-131-2/+25
* gettextureimage: verify cube map is completeJuan A. Suarez Romero2018-04-131-9/+14
* gettextsubimage: verify zoffset and depth are correctJuan A. Suarez Romero2018-04-131-2/+2
* mesa: free debug messages when destroying the debug stateTimothy Arceri2018-04-131-22/+23
* mesa: fix x86 buildsTimothy Arceri2018-04-131-0/+1
* Fix make checkMarek Olšák2018-04-121-0/+1
* Fix scons buildMarek Olšák2018-04-127-1/+13
* mesa: include mtypes.h lessMarek Olšák2018-04-12177-367/+477
* mesa: include dispatch.h lessMarek Olšák2018-04-1220-20/+0
* radv: Implement VK_EXT_vertex_attribute_divisor.Bas Nieuwenhuizen2018-04-126-11/+50
* ac/surface: Allow S swizzle for displayable surfaces.Bas Nieuwenhuizen2018-04-121-2/+5
* broadcom/vc5: Fix a stray '`' in a comment.Eric Anholt2018-04-121-1/+1
* broadcom/vc5: Update the UABI for in/out syncobjsEric Anholt2018-04-129-90/+55
* broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2018-04-122-11/+0
* broadcom/vc5: Drop the throttling code.Eric Anholt2018-04-121-9/+0
* broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt2018-04-121-28/+29
* broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt2018-04-121-13/+13
* broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt2018-04-121-23/+13
* broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt2018-04-121-5/+16
* broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt2018-04-121-0/+8
* broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt2018-04-121-2/+4
* st/va: add VP9 config to enable profile2Leo Liu2018-04-122-1/+5
* radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu2018-04-121-1/+2
* radeon/vcn: add VP9 profile2 supportLeo Liu2018-04-121-0/+16
* vl: add VP9 profile2 supportLeo Liu2018-04-122-1/+3
* st/va: add VP9 config to enable profile0Leo Liu2018-04-122-1/+5
* st/va: parse VP9 uncompressed frame headerLeo Liu2018-04-123-1/+239
* st/va: add slice parameter handling for VP9Leo Liu2018-04-121-1/+24
* st/va: add picture parameter handling for VP9Leo Liu2018-04-121-1/+51
* st/va: add handles for VP9 buffersLeo Liu2018-04-125-2/+54
* st/va: add VP9 picture to contextLeo Liu2018-04-122-0/+5
* radeonsi: cap VP9 support to progressive bufferLeo Liu2018-04-121-0/+2
* radeonsi: cap VP9 support to RavenLeo Liu2018-04-121-0/+4
* radeon/vcn: add VP9 context bufferLeo Liu2018-04-121-0/+26
* radeon/vcn: get VP9 msg bufferLeo Liu2018-04-122-1/+176
* radeon/vcn: fill probability table to prob buffersLeo Liu2018-04-121-0/+38
* radeon/vcn: add VP9 message buffer interfaceLeo Liu2018-04-121-0/+134
* radeon/vcn: add VP9 prob table bufferLeo Liu2018-04-122-18/+37
* vl: add VP9 probability tablesLeo Liu2018-04-123-1/+588
* radeon/vcn: add VP9 dpb buffer sizeLeo Liu2018-04-121-0/+6
* radeon/vcn: add VP9 stream type for decoderLeo Liu2018-04-122-0/+4
* vl: add VP9 picture descriptionLeo Liu2018-04-121-0/+94
* vl: add VP9 profile0 and formatLeo Liu2018-04-122-2/+7
* radv: fix radv_layout_dcc_compressed() when image doesn't have DCCSamuel Pitoiset2018-04-121-1/+1
* radv: add radv_decompress_resolve_{subpass}_src() helpersSamuel Pitoiset2018-04-124-54/+73
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