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* st/va: fix incorrect argument in vl_compositor_cleanupNayan Deshmukh2017-01-051-1/+1
* swr: remove unneeded llvm version checkTim Rowley2017-01-051-4/+0
* swr: fix windows build breakGeorge Kyriazis2017-01-052-4/+7
* radeonsi: update clip_regs if clip_disable changes to fix a hangMarek Olšák2017-01-051-0/+5
* st/mesa: enable GLSLOptimizeConservatively for drivers that want itMarek Olšák2017-01-051-0/+2
* glsl_to_tgsi: do fewer optimizations with GLSLOptimizeConservativelyMarek Olšák2017-01-051-9/+67
* mesa: add gl_constants::GLSLOptimizeConservativelyMarek Olšák2017-01-054-10/+37
* gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELYMarek Olšák2017-01-0517-0/+19
* glsl: run do_lower_jumps properly in do_common_optimizationsMarek Olšák2017-01-053-10/+3
* i965: Print VS output VUE map in Vulkan too.Kenneth Graunke2017-01-052-3/+5
* i965: Fix last slot calculationsKenneth Graunke2017-01-051-3/+13
* docs: Mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as done for i965/hsw+Iago Toral Quiroga2017-01-051-2/+2
* docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.Iago Toral Quiroga2017-01-051-0/+2
* i965: add a kernel_features bitfield to intel screenIago Toral Quiroga2017-01-055-22/+59
* i965/gen7: Enable OpenGL 4.0 in Haswell when supportedIago Toral Quiroga2017-01-052-1/+4
* i965: get rid of brw->can_do_pipelined_register_writesIago Toral Quiroga2017-01-055-10/+10
* i965: Move the pipelined test for SO register access to the screenChris Wilson2017-01-054-73/+103
* i965/disasm: remove printing hstride and width in align16 DF source regionsSamuel Iglesias Gonsálvez2017-01-051-4/+1
* vec4: use DIM instruction when loading DF immediates in HSWSamuel Iglesias Gonsálvez2017-01-051-0/+9
* glcpp: Remove illegal characters from testsCarl Worth2017-01-046-6/+6
* glcpp: Exhaustively test all legal characters in GLSLCarl Worth2017-01-042-0/+154
* glcpp: Allow vertical tab and form feed characters in GLSLCarl Worth2017-01-041-1/+1
* glcpp: Add testing for no space between macro name and replacement listCarl Worth2017-01-042-0/+116
* spirv: compute push constant access offset & rangeLionel Landwerlin2017-01-042-14/+65
* spirv: move block_size() definitionLionel Landwerlin2017-01-041-48/+48
* va: call texture_get_handle while the mutex is being heldMarek Olšák2017-01-041-2/+5
* vdpau: call texture_get_handle while the mutex is being heldMarek Olšák2017-01-042-6/+13
* radeonsi: capitalize VM hex addr when dumping buffer listSamuel Pitoiset2017-01-041-1/+1
* i965: remove unused brwInitVtbl declarationTapani Pälli2017-01-041-5/+0
* i965: remove brw_context dependency from intel_batchbuffer_init()Iago Toral Quiroga2017-01-043-28/+36
* i965: make intel_batchbuffer_free() take a batchbuffer as argumentIago Toral Quiroga2017-01-043-6/+6
* i965: make intel_batchbuffer_emit_dword() take a batchbuffer as argumentIago Toral Quiroga2017-01-042-12/+12
* i965: Make intel_bachbuffer_reloc() take a batchbuffer argumentIago Toral Quiroga2017-01-043-15/+15
* nir: fix loop iteration count calculation for floatsTimothy Arceri2017-01-041-2/+2
* gallium/hud: add a path separator between dump directory and filenameEdmondo Tommasina2017-01-031-1/+2
* r600/sb: Fix loop optimization related hangs on egHeiko Przybyl2017-01-036-30/+68
* editorconfig: Fix up the tab rendering width.Eric Anholt2017-01-031-0/+1
* meta: Disable dithering during glGenerateMipmapChad Versace2017-01-031-0/+1
* doc/features.txt: update for freedrenoRomain Failliot2017-01-031-19/+19
* i965: Remove perf monitor/query backendRobert Bragg2017-01-036-1597/+1
* vl/zscan: fix "Fix trivial sign compare warnings"Christian König2017-01-031-1/+1
* st/va: error handlingNayan Deshmukh2017-01-031-3/+15
* st/vdpau: error handlingNayan Deshmukh2017-01-033-15/+50
* vl/compositor: implement error handlingNayan Deshmukh2017-01-032-3/+12
* i965/vec4: enable ARB_gpu_shader_fp64 for HaswellIago Toral Quiroga2017-01-031-0/+3
* i965/vec4: adjust spilling costs for 64-bit registers.Iago Toral Quiroga2017-01-031-2/+13
* i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destinationIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit accessIago Toral Quiroga2017-01-031-0/+24
* i965/vec4: support basic spilling of 64-bit registersIago Toral Quiroga2017-01-031-6/+28
* i965/vec4: run scalarize_df() after spillingIago Toral Quiroga2017-01-031-0/+18
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