aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle2017-04-1417-0/+19
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* configure.ac: add --enable-sanitize optionNicolai Hähnle2017-04-141-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable code sanitizers by adding -fsanitize=$foo flags for the compiler and linker. In addition, this also disables checking for undefined symbols: running the address sanitizer requires additional symbols which should be provided by a preloaded libasan.so (preloaded for hooking into malloc & friends globally), and the undefined symbols check gets tripped up by that. Running the tests works normally via `make check`, but shows additional failures with the address sanitizer due to memory leaks that seem to be mostly leaks in the tests themselves. I believe those failures should really be fixed. In the mean-time, you can set export ASAN_OPTIONS=detect_leaks=0 to only check for more serious error types. v2: - fail reasonably when an unsupported sanitize flag is given (Eric Engestrom) Reviewed-by: Bartosz Tomczyk <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv/cmd_buffer: Flush the VF cache at the top of all primariesJason Ekstrand2017-04-141-0/+12
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Cc: "13.0 17.0" <[email protected]>
* anv/blorp: Flush the texture cache in UpdateBufferJason Ekstrand2017-04-141-0/+7
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Cc: "13.0 17.0" <[email protected]>
* anv: Limit VkDeviceMemory objects to 2GBJason Ekstrand2017-04-141-0/+20
| | | | Reviewed-by: Juan A. Suarez Romero <[email protected]>
* intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand2017-04-141-64/+50
| | | | | | | This makes it much easier to throw together a bit of dynamic state. It also automatically handles flushing so you don't accidentally forget. Reviewed-by: Alejandro Piñeiro <[email protected]>
* swr: Enable MSAA in OpenSWR software rendererBruce Cherniak2017-04-146-25/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables multisample antialiasing in the OpenSWR software renderer. MSAA is a proof-of-concept/work-in-progress with bug fixes and performance on the way. We wanted to get the changes out now to allow several customers to begin experimenting with MSAA in a software renderer. So as not to impact current customers, MSAA is turned off by default - previous functionality and performance remain intact. It is easily enabled via environment variables, as described below. It has only been tested with the glx-lib winsys. The intention is to enable other state-trackers, both Windows and Linux and more fully support FBOs. There are 2 environment variables that affect behavior: * SWR_MSAA_FORCE_ENABLE - force MSAA on, for apps that are not designed for MSAA... Beware, results will vary. This is mainly for testing. * SWR_MSAA_MAX_SAMPLE_COUNT - sets maximum supported number of samples (1,2,4,8,16), or 0 to disable MSAA altogether. (The default is currently 0.) Reviewed-by: George Kyriazis <[email protected]>
* swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supportedBruce Cherniak2017-04-141-2/+1
| | | | | | | | | Removed unnecessary and probably wrong PIPE_BIND_SCANOUT and PIPE_BIND_SHARED flags in favor of check on single PIPE_BIND_DISPLAY_TARGET flag. Reference llvmpipe change <bee4c7718a3bd57e3d99f0913d9081cd13fe5fd> Reviewed-by: Tim Rowley <[email protected]>
* swr: Align swr_context allocation to SIMD alignment.Bruce Cherniak2017-04-141-2/+5
| | | | | | | | | The context now contains SIMD vectors which must be aligned (specifically samplePositions in the rastState in the derived state). Failure to align can result in segv crash on unaligned memory access in vector instructions. Reviewed-by: Tim Rowley <[email protected]>
* swr: update gallium driver docsTim Rowley2017-04-142-6/+12
| | | | | | v2: add back scons section, mention additional built swr libraries Reviewed-by: Bruce Cherniak <[email protected]>
* radv: remove irrelevant commentGrazvydas Ignotas2017-04-141-1/+1
| | | | | | | A leftover from anv. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: report timestampPeriod correctlyGrazvydas Ignotas2017-04-142-2/+2
| | | | | | | | | | | | The kernel returns frequency in kHz, so to convert to nanosecond interval that Vulkan uses the dividend should be 1000000.0 and not 100000.0. This fixes the GPU graph in DOOM and matches the amdgpu-pro blob. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/print: add compute shader infoRob Clark2017-04-141-0/+13
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* gallium/docs: small correction about register files for atomicsRob Clark2017-04-141-2/+4
| | | | | | | | These can operate on MEMORY[], in addition to BUFFER[] and IMAGE[] Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno: enable draw/batch reordering by defaultRob Clark2017-04-142-3/+3
| | | | | | | | Probably should have flipped the switch a long time ago, since it doesn't seem to cause any problems and is a nice perf boost in a number of cases. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small re-orderRob Clark2017-04-141-24/+23
| | | | | | | Small re-order of switch statement to handled op-code categories in order. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move 'keeps' to block levelRob Clark2017-04-145-20/+22
| | | | | | | For things like SSBOs and atomics we'll want to track this at a block level. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: convert dynamic arrays to rallocRob Clark2017-04-143-14/+8
| | | | | | | Want to move one of these under ir3_block, so that gives a reason to migrate the remaining malloc/realloc to ralloc. Signed-off-by: Rob Clark <[email protected]>
* swr: add linux to scons buildGeorge Kyriazis2017-04-142-7/+2
| | | | | | Make swr compile for both linux and windows. Reviewed-by: Tim Rowley <[email protected]>
* radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.Bas Nieuwenhuizen2017-04-142-7/+7
| | | | | | | v2: Also convert the calculations. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]>
* docs: Update MESA_shader_integer_functions spec to version 3.Kenneth Graunke2017-04-131-6/+8
| | | | | | | | | | | | | When publishing this spec on the OpenGL ES registry, Jon Leech noticed that it didn't actually mention what the ES dependencies and interactions were. I looked at extensions_table.h and noted that we expose it in ES 3.0 contexts, and he added the obvious spec texts. The updated copy also contains our official extension number. https://github.com/KhronosGroup/OpenGL-Registry/issues/3 Acked-by: Matt Turner <[email protected]>
* radv: Set descriptor set limits.Bas Nieuwenhuizen2017-04-131-15/+29
| | | | | | | Properly and with comments this time. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Increase integer sizes in descriptor sets.Bas Nieuwenhuizen2017-04-131-8/+8
| | | | | | | | Needed if we want to allow them taking more than 64 KiB. The calculations of these already used 32 bits. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: support S8_UINT as a depth/stencil format.Dave Airlie2017-04-141-1/+1
| | | | | | | This enables a bunch of NotSupported CTS tests. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump maxGeometryShaderInvocations.Dave Airlie2017-04-141-1/+1
| | | | | | | | | This bumps it to the same level as amdgpu-pro, it also moves a bunch of dEQP-VK.geometry.instanced.* from NotSupported to Pass. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/nine: Fix support for ps 1.4 dw and dz modifiersAxel Davy2017-04-131-2/+2
| | | | | | | | | | | RCP was used incorrectly to support NINED3DSPSM_DW and NINED3DSPSM_DZ. src.x was used as input instead of src.w or src.z. Fixes: https://github.com/iXit/Mesa-3D/issues/271 Signed-off-by: Axel Davy <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* clover: Add missing include to compat headerJan Vesely2017-04-131-0/+1
| | | | | | | | | | Fixes build failure with LLVM 4 Fixes: a981e68c26dc4079a335101da0033185030207f6 (clover: Fix build against clang SVN >= r299965) Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* gallium/radeon: never use staging buffers with AMD_pinned_memoryNicolai Hähnle2017-04-131-2/+16
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle2017-04-133-4/+23
| | | | | | | | | | | | | | | | | | | gl_BaseVertex is supposed to be 0 in non-indexed draws. Unfortunately, the way they're implemented, the VGT always generates indices starting at 0, and the VS prolog adds the start index. There's a VGT_INDX_OFFSET register which causes the VGT to start at a driver-defined index. However, this register cannot be written from indirect draws. So fix this unlikely case by setting a bit to tell the VS whether the draw is indexed or not, so that gl_BaseVertex can be adjusted accordingly when used. Fixes a bug in KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters.* Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle2017-04-135-27/+18
| | | | | | v2: fix incorrect change in get_tcs_out_patch_stride Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle2017-04-133-9/+14
| | | | | | Avoid conflicts when merging various VS state bits. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle2017-04-136-2/+27
| | | | | | We will merge other derived state information into this register. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract derived tess state emit to higher levelNicolai Hähnle2017-04-131-6/+7
| | | | | | | Especially with subsequent changes, this makes it easier to see the sequence of state emits at the higher level. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: drop support for TGSI_SEMANTIC_VERTEXID_NOBASENicolai Hähnle2017-04-131-2/+3
| | | | | | It is unused. Reviewed-by: Marek Olšák <[email protected]>
* radv: Add more trace points.Bas Nieuwenhuizen2017-04-132-0/+3
| | | | | | | | | | | Most trace points happen after an operation, so add a trace point at the start of the command buffer. Furthermore, add one after a CmdUpdateBuffer using CP_DMA as that didn't emit one yet. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Ignore CmdUpdateBuffer with size 0.Bas Nieuwenhuizen2017-04-131-0/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Enable query inheritance.Bas Nieuwenhuizen2017-04-131-1/+1
| | | | | | | | | | | | | | timestamp and pipeline_statistics only do something on begin & end, so they don't need any action. Occlusion queries only do something to enable/disable and that register is set nowhere else so that doesn't need extra support either. (We technically should fix it to update the reg with the number of samples, but that hasn't happened yet, so we only change it to enable/disable counting) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: enable variableMultisampleRate.Bas Nieuwenhuizen2017-04-131-1/+1
| | | | | | | | | This is only relevant with 0 attachments. In that case we do nothing on subpass switch already, and the pipeline is the authoritative source of the number of samples, so this shouldn't change anything. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium/hud: set the dump file streams to line bufferedEdmondo Tommasina2017-04-131-0/+2
| | | | | | | | Flush the HUD value streams to the dump files after every newline. v2: check that fopen succeeded (Julien) Reviewed-and-Tested-by: Julien Isorce <[email protected]>
* radv: fix stencil regression since new addrlib importDave Airlie2017-04-132-1/+9
| | | | | | | | | | The addrlib import meant we'd return after we attempted to setup the no stencil bits for an S8_UINT, now we break and use the stencil level info when creating stencil DB info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: allocate thin textures as linear.Dave Airlie2017-04-131-0/+7
| | | | | | | | | | This is ported from radeonsi, and avoids the bug in the addrlib code. This should probably be something addrlib does for us, but for now this fixes the regression without changing addrlib and aligns us with radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: add missing ir_unop_*/ir_binop_* in visit_leave()Samuel Pitoiset2017-04-131-0/+3
| | | | | | | | | | | | Fixes the following Clang warnings. brw_fs_channel_expressions.cpp:219:12: warning: enumeration values 'ir_unop_ballot', 'ir_unop_read_first_invocation', and 'ir_binop_read_invocation' not handled in switch [-Wswitch] switch (expr->operation) { ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: fix wrong comparison in update_framebuffer_state()Samuel Pitoiset2017-04-131-4/+4
| | | | | | | | | | | | | | state_tracker/st_atom_framebuffer.c:208:27: warning: comparison of constant 4294967295 with expression of type 'uint16_t' (aka 'unsigned short') is always false [-Wtautological-constant-out-of-range-compare] if (framebuffer->width == UINT_MAX) ~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~ state_tracker/st_atom_framebuffer.c:210:28: warning: comparison of constant 4294967295 with expression of type 'uint16_t' (aka 'unsigned short') is always false [-Wtautological-constant-out-of-range-compare] if (framebuffer->height == UINT_MAX) ~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~ 2 warnings generated. Fixes: eb0fd0e5f86 ("gallium: decrease the size of pipe_framebuffer_state - 96 -> 80 bytes") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon: fix duplicate 'const' specifierSamuel Pitoiset2017-04-132-2/+2
| | | | | | | | | | | | | | Fixes the following Clang warning. In file included from radeon_debug.c:32: ./radeon_common_context.h:500:19: warning: duplicate 'const' declaration specifier [-Wduplicate-decl-specifier] extern const char const *radeonVendorString; v2: - do not remove the duplicate 'const' qualifier, fix it Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* svga: remove unused vmw_dri1_intersect_src_bbox()Samuel Pitoiset2017-04-131-32/+0
| | | | | | | | | | | | Fixes the following Clang warning. vmw_screen_dri.c:130:1: warning: unused function 'vmw_dri1_intersect_src_bbox' [-Wunused-function] vmw_dri1_intersect_src_bbox(struct drm_clip_rect *dst, ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: remove unused subpixel_snap() and fixed_to_float()Samuel Pitoiset2017-04-131-6/+3
| | | | | | | | | | | | | | | | Fixes the following Clang warnings. lp_setup_tri.c:55:1: warning: unused function 'subpixel_snap' [-Wunused-function] subpixel_snap(float a) ^ lp_setup_tri.c:61:1: warning: unused function 'fixed_to_float' [-Wunused-function] fixed_to_float(int a) ^ v2: - do not remove subpixel_snap() (use !PIPE_ARCH_SSE instead) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* softpipe: remove unused sp_exec_fragment_shader()Samuel Pitoiset2017-04-131-8/+0
| | | | | | | | | | | | Fixes the following Clang warning. sp_fs_exec.c:56:1: warning: unused function 'sp_exec_fragment_shader' [-Wunused-function] sp_exec_fragment_shader(const struct sp_fragment_shader_variant *var) ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: remove unused quad_shade_stage()Samuel Pitoiset2017-04-131-8/+0
| | | | | | | | | | | | Fixes the following Clang warning. sp_quad_fs.c:60:1: warning: unused function 'quad_shade_stage' [-Wunused-function] quad_shade_stage(struct quad_stage *qs) ^ 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: remove unused get_texel_quad_2d()Samuel Pitoiset2017-04-131-17/+0
| | | | | | | | | | | | | Fixes the following Clang warning. sp_tex_sample.c:802:1: warning: unused function 'get_texel_quad_2d' [-Wunused-function] get_texel_quad_2d(const struct sp_sampler_view *sp_sview, ^ CC sp_tile_cache.lo 1 warning generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* trace: remove some unused trace_dump_tag*() functionsSamuel Pitoiset2017-04-131-52/+0
| | | | | | | | | | | | | | | | | | | Fixes the following Clang warnings. tr_dump.c:137:1: warning: unused function 'trace_dump_tag' [-Wunused-function] trace_dump_tag(const char *name) ^ tr_dump.c:168:1: warning: unused function 'trace_dump_tag_begin2' [-Wunused-function] trace_dump_tag_begin2(const char *name, ^ tr_dump.c:187:1: warning: unused function 'trace_dump_tag_begin3' [-Wunused-function] trace_dump_tag_begin3(const char *name, ^ CC tr_texture.lo 3 warnings generated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 04:36:53 +0000