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* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-06-111-5/+1
| | | | | | | | | | | | | This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043. The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4. interpolation.lines_wide" test appears to be broken on Cherryview when we expose line widths greater than 12.0. I'm not sure why. For now, just go back to the limits we used on older platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902 Acked-by: Matt Turner <[email protected]>
* i965: Re-index SSA definitions before printing NIR code.Kenneth Graunke2015-06-111-0/+6
| | | | | | | | | | This makes the SSA definitions use sequential numbers (0, 1, 2, ...) instead of seemingly random ones. There's not much point normally, but it makes debug output much easier to read. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* gallium: remove explicit values from PIPE_CAP_ enumsBrian Paul2015-06-111-98/+98
| | | | | | | The other PIPE_CAPF_ and PIPE_SHADER_CAP_ enums don't have explicit values. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa/main: Don't use ONCE_FLAG_INIT as a r-value.Jose Fonseca2015-06-111-1/+2
| | | | | | | | | It should only be used as an initializer expression. Trivial, and fixes Windows builds. Nevertheless, overwriting an once_flag like this seems dangerous and should be revised.
* i965/gen8: Fix antialiased line rendering with width < 1.5Iago Toral Quiroga2015-06-114-49/+30
| | | | | | | | | | | The same fix Marius implemented for gen6 (commit a9b04d8a) and gen7 (commit 24ecf37a). Also, we need the same code to handle special cases of line width in gen6, gen7 and now gen8, so put that in the helper function we use to compute the line width. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: fix constructing a vector from a matrixMartin Peres2015-06-111-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, the following constructs (not an extensive list) would crash mesa: - mat2 foo = mat2(1); vec4 bar = vec4(foo); - mat3 foo = mat3(1); vec4 bar = vec4(foo); - mat3 foo = mat3(1); ivec4 bar = ivec4(foo); The first case is explicitely allowed by the GLSL spec, as seen on page 101 of the GLSL 4.40 spec: "vec4(mat2) // the vec4 is column 0 followed by column 1" The other cases are implicitely allowed also. The actual changes are quite minimal. We first split each column of the matrix to a list of vectors and then use them to initialize the vector. An additional check to make sure that we are not trying to copy 0 elements of a vector fix the (i)vec4(mat3) case as the last vector (3rd column) is not needed at all. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Martin Peres <[email protected]>
* mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1Tapani Pälli2015-06-112-2/+18
| | | | | | | | | | (increases ES31-CTS.draw_indirect.basic.* passing tests) v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/main: avoid null access in format_array_table_init()Juha-Pekka Heikkila2015-06-111-0/+10
| | | | | | | | If _mesa_hash_table_create failed we'd get null pointer. Report error and go away. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa/main: Remove _mesa_HashClone()Juha-Pekka Heikkila2015-06-112-31/+0
| | | | | | | | I didn't find this being used anywhere. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: do_blit_drawpixels: decode array formatsAlexander Monakov2015-06-111-0/+2
| | | | | | | | | | | | Correct a regression introduced by commit 922c0c9fd526 by converting "array format", if received from _mesa_format_from_format_and_type, to mesa_format. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Alexander Monakov <[email protected]> Tested-by: AnAkkk <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: do not round line width when multisampling or antialiaing are enabledIago Toral Quiroga2015-06-115-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit fe74fee8fa721a we rounded the line width to the nearest integer to match the GLES3 spec requirements stated in section 13.4.2.1, but that seems to break a dEQP test that renders wide lines in some multisampling scenarios. Ian noted that the Open 4.4 spec has the following similar text: "The actual width of non-antialiased lines is determined by rounding the supplied width to the nearest integer, then clamping it to the implementation-dependent maximum non-antialiased line width." and suggested that when ES removed antialiased lines, they removed "non-antialised" from that paragraph but probably should not have. Going by that note, this patch restricts the quantization implemented in fe74fee8fa721a only to regular aliased lines. This seems to keep the tests fixed with that commit passing while fixing the broken test. v2: - Drop one of the clamps (Ken, Marius) - Add a rule to prevent advertising line widths that when rounded go beyond the limits allowed by the hardware (Ken) - Update comments in the code accordingly (Ian) - Put the code in a utility function (Ian) Fixes: dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.6" <[email protected]>
* i965: Momentarily pretend to support ARB_texture_stencil8 for blits.Kenneth Graunke2015-06-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell's stencil blitting code attempts to bind a renderbuffer as a texture, using dd->BindRenderbufferTexImage(). This calls _mesa_init_teximage_fields(), which then attempts to set img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which assert fails if internalFormat is GL_STENCIL_INDEX8 but ARB_texture_stencil8 is unsupported. To work around this, just pretend to support the extension momentarily, during the blit. Meta has already munged a variety of other things in the context (including the API!), so it's not that much worse than what we're already doing. Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47 (mesa/teximage: use correct extension for accept stencil texture.). v2: Add an XXX comment explaining the situation (requested by Jason Ekstrand and Martin Peres), and an assert that we don't support the extension so we remember to remove this hack (requested by Neil Roberts). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* llvmpipe: simplify lp_resource_copy()Brian Paul2015-06-101-59/+2
| | | | | | | | | | Just implement it in terms of util_resource_copy_region(). Both the original code and util_resource_copy_region() boil down to mapping, calling util_copy_box() and unmapping. No piglit regressions. This will also help to implement GL_ARB_copy_image. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: add GL_RED, GL_RG support for floating point texturesTapani Pälli2015-06-101-3/+34
| | | | | | | | | | | | | | | | | Mesa supports EXT_texture_rg and OES_texture_float. This patch adds support for using unsized enums GL_RED and GL_RG for floating point targets and writes proper checks for internalformat when format is GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT. Later, internalformat will get adjusted by adjust_for_oes_float_texture after these checks. v2: simplify to check vs supported enums v3: follow the style and break out if internalFormat ok (Kenneth) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748 Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: allow unsized formats GL_RG, GL_RED for GLES 3.0 with half floatTapani Pälli2015-06-101-0/+4
| | | | | | | | v2: && -> ||, we enable on gles3 or if ARB_texture_rg is enabled Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748 Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: remove restriction on unsized arrays in GLSL ES 3.10Timothy Arceri2015-06-101-1/+9
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* st/dri: check pscreen is valid before querying paramDave Airlie2015-06-101-1/+1
| | | | | | | | | we don't check the validity of pscreen until dri_init_screen_helper hit this trying to init glamor on a device with no driver (udl). Acked-by: Michel Dänzer <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau: set imported buffers to what the kernel gives usDave Airlie2015-06-101-1/+1
| | | | | | | | | | | | | When we import a dma-buf fd from another driver the kernel gives us the right info, and this trashes it. Convert the kernel bo flags into the domain flags. This helps getting reverse prime and glamor working. Cc: [email protected] Acked-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vc4: Drop qir include from vc4_screen.hEric Anholt2015-06-091-1/+1
| | | | | We didn't need any of it except for the list header, and qir.h pulls in nir.h, which is not really interesting to winsys.
* vc4: Drop subdirectory in vc4 build.Eric Anholt2015-06-095-50/+5
| | | | | Just because we put the source in a subdir, doesn't mean we need helper libraries in the build. This will also simplify the Android build setup.
* vc4: Update to current kernel validation code.Eric Anholt2015-06-093-35/+37
| | | | | After profiling on real hardware, I found a few ways to cut down the kernel overhead.
* android: build with libcxx on android lollipopChih-Wei Huang2015-06-095-2/+11
| | | | | | | | On Lollipop, apparently stlport is gone and libcxx must be used instead. We still support stlport when building on earlier android releases. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: enable the radeonsi driverChih-Wei Huang2015-06-096-0/+40
| | | | | | | | | | | | | | | Based on the nice work of Paulo Sergio Travaglia <[email protected]>. The main modifications are: - Include paths for LLVM header files and shared/static libraries - Set C++ flag "c++11" to avoid compiling errors on LLVM header files - Set defines for LLVM - Add GALLIVM source files - Changes path of libelf library for lollipop Signed-off-by: Chih-Wei Huang <[email protected]> Acked-by: Eric Anholt <[email protected]>
* android: generate files by $(call es-gen)Chih-Wei Huang2015-06-091-4/+12
| | | | | | | | | | | | | Use the pre-defined macro es-gen to generate new added files instead of writing new rules manually. The handmade rules that may generate the files before the directory is created result in such an error: /bin/bash: out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c: No such file or directory make: *** [out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c] Error 1 Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: try to load gallium_dri.so directlyChih-Wei Huang2015-06-091-0/+9
| | | | | | | | | | | This avoids needing hardlinks between all of the DRI driver .so names, since we're the only loader on the system. v2: Add early exit on success (like previous block) and log message on failure. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: Depend on gallium_dri from EGL, instead of linking in gallium.Chih-Wei Huang2015-06-093-85/+5
| | | | | | | | | | | | The Android gallium build used to use gallium_egl, which was removed back in March. Instead, we will now use a normal Mesa libEGL loader with dlopen()ing of a DRI module. v2: add a clean step to rebuild all dri modules properly. v3: Squish the 2 patches doing this together (change by anholt). Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: add rules to build a gallium_dri.soChih-Wei Huang2015-06-094-2/+189
| | | | | | | This single .so includes all of the enabled gallium drivers. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: add rules to build gallium/state_trackers/driChih-Wei Huang2015-06-092-2/+67
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: export more dirs from libmesa_dri_commonChih-Wei Huang2015-06-091-1/+3
| | | | | | | | The include paths of libmesa_dri_common are also used by modules that need libmesa_dri_common. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: loader: export the path to be includedChih-Wei Huang2015-06-092-1/+2
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen9: Use raw PS invocation count for queriesBen Widawsky2015-06-091-1/+1
| | | | | | | | | | | | Previously the number needed to be divided by 4 to get the proper results. Now the hardware does the right thing. Through experimentation it seems Braswell (CHV) does also need the division by 4. Fixes piglit test: arb_pipeline_statistics_query-frag Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* glsl: fix comment typo: s/accpet/accept/Brian Paul2015-06-091-1/+1
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* mesa: remove some MAX_NV_FRAGMENT_PROGRAM_* macrosBrian Paul2015-06-092-13/+4
| | | | | | | GL_NV_fragment_program support was removed a while ago. This is just some clean-up. Reviewed-by: Matt Turner <[email protected]>
* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-092-16/+13
| | | | | | | These are helpers that only exist in this one file. No reason to put them in the visitor. Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-092-3/+17
| | | | | | | | | | | | | Previously, we just put the message for the EOT send as high in the file as it would go. This is because the register pre-filling hardware will stop all over the early registers in the file in preparation for the next thread while you're still sending the last message. However, if something happens to spill, then the MRF hack interferes with the EOT send message and, if things aren't scheduled nicely, will stomp on it. Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520 Reviewed-by: Neil Roberts <[email protected]>
* rtasm: Generalize executable memory allocator to all Unices.Jose Fonseca2015-06-091-1/+1
| | | | | | | | | | We're only using fairly portable standard Unix calls here, so might as well save ourselves future trouble by enabling on all Unices by default. https://bugs.freedesktop.org/show_bug.cgi?id=90904 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965/fs: Drop fs_inst::force_uncompressed.Francisco Jerez2015-06-091-1/+0
| | | | | | This is now unused. Saves a whole bit of memory per instruction. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dead IR construction code from the visitor.Francisco Jerez2015-06-094-439/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_cmod_propagation to the IR builder.Francisco Jerez2015-06-091-52/+50
| | | | | | | v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_saturate_propagation to the IR builder.Francisco Jerez2015-06-091-35/+34
| | | | | | v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR texturing instructions to the IR builder.Francisco Jerez2015-06-092-5/+6
| | | | | | v2: Don't remove assignments of base_ir just yet. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR intrinsics to the IR builder.Francisco Jerez2015-06-092-41/+42
| | | | | | v2: Use fs_builder::SEL instead of ::emit. Use set_condmod(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR ALU instructions to the IR builder.Francisco Jerez2015-06-093-99/+99
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR control flow to the IR builder.Francisco Jerez2015-06-092-12/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR variable handling to the IR builder.Francisco Jerez2015-06-091-11/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR emit_percomp() to the IR builder.Francisco Jerez2015-06-092-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate CS terminate message to the IR builder.Francisco Jerez2015-06-091-3/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate VS output writes to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS framebuffer writes to the IR builder.Francisco Jerez2015-06-093-34/+35
| | | | | | | | | | | | | | The explicit call to fs_builder::group() in emit_single_fb_write() is required by the builder (otherwise the assertion in fs_builder::emit() would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE instructions are in some cases emitted with a non-native execution width. The previous code would always use the channel enables for the first quarter, which is dubious but probably worked in practice because FB writes are never emitted inside non-uniform control flow and we don't pass the kill-pixel mask via predication in the cases where we have to fall-back to SIMD8 writes. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS alpha test to the IR builder.Francisco Jerez2015-06-091-5/+5
| | | | Reviewed-by: Matt Turner <[email protected]>
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