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* mesa: Add SSE 4.1 optimisation for glDrawElements.Timothy Arceri2014-11-066-5/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes use of SSE 4.1 to speed up compute of min and max elements. Callgrind cpu usage results from pts benchmarks: Openarena 0.8.8: 3.67% -> 1.03% UrbanTerror: 2.36% -> 0.81% V5: - actually make use of the optimisation in android (Emil Velikov) - set a better array size limit for using SSE and added TODO V4: - fixed bugs with incrementing pointer and updating counters V3: - Removed sse_minmax.c from Makefile.sources - handle the first few values without SSE until the pointer is aligned and use _mm_load_si128 rather than _mm_loadu_si128 - guard the call to the SSE code better at build time V2: - removed GL* types - use _mm_store_si128() rather than _mm_store_ps() - add runtime check for SSE - use aligned attribute for local mix/max - bunch of tidyups Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Timothy Arceri <[email protected]>
* i965: Remove non-existent vertical strides from array.Matt Turner2014-11-061-1/+1
| | | | | | These never existed, as far as I can tell. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert stride/width/execution size macros into enums.Matt Turner2014-11-061-28/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove force uncompressed stack.Matt Turner2014-11-063-27/+0
| | | | | | Last use was in shader_time. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use execution size of 1 for some shader_time operations.Matt Turner2014-11-061-1/+1
| | | | | | The ADDs depended on dispatch_width, which really isn't what we wanted. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use mov(4) instructions to read timestamp.Matt Turner2014-11-061-5/+4
| | | | We only want fields 0-2.
* clover: Fix build after llvm r221375Jan Vesely2014-11-061-0/+4
| | | | | Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Jan Vesely <[email protected]>
* egl_dri2: do not leak dri2_dpy->driver_configsEmil Velikov2014-11-061-0/+4
| | | | | | | | Walk through the list and free each config, and finally free the list itself. Freeing approx 20KiB of memory, according to valgrind. Inspired by a similar patch by enpeng xu. Signed-off-by: Emil Velikov <[email protected]>
* ilo: add two missing headers to the sources listEmil Velikov2014-11-061-0/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* Releasing a surfaceless EGL context doesn't release underlying DRI context.Alexandros Frantzis2014-11-061-2/+6
| | | | | | | | | | | | | | | | | | driUnbindContext() checks for valid drawables before calling the driver unbind function. In case of Surfaceless contexts, the drawables are always Null and we end up not releasing the underlying DRI context. Moving the call to the driver function before the drawable validity checks fixes things. Steps to trigger this bug are following: - create surfaceless context and make it current - make some other context current - {another thread} destroy surfaceless context - make another context current Signed-off-by: Alexandros Frantzis <[email protected]> Signed-off-by: Kalyan Kondapally <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74563
* ilo: let ilo_shader_compile_cs() return a dummy shaderChia-I Wu2014-11-061-1/+185
| | | | | | | | The dummy shader sends an EOT message to end itself. There are many more works need to be done on the compiler side before we can advertise PIPE_CAP_COMPUTE. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: hook up launch_grid()Chia-I Wu2014-11-061-3/+73
| | | | | | | All we need to do is to upload the input data and call ilo_render_emit_launch_grid() with space checking. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add ilo_render_emit_launch_grid()Chia-I Wu2014-11-068-2/+621
| | | | | | | ilo_render_emit_launch_grid() emits all the hardware states needed for a launch_grid() call. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: improve media command helpersChia-I Wu2014-11-061-71/+141
| | | | | | They were written for Gen6 but mostly untested. Make them work for Gen7+. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: disassemble DP DC messagesChia-I Wu2014-11-061-2/+140
| | | | Signed-off-by: Chia-I Wu <[email protected]>
* ilo: disassemble TS messagesChia-I Wu2014-11-061-0/+35
| | | | Signed-off-by: Chia-I Wu <[email protected]>
* ilo: update genhw headers for media pipelineChia-I Wu2014-11-067-148/+479
| | | | Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add ilo_finalize_compute_states()Chia-I Wu2014-11-062-0/+37
| | | | | | It updates the handles of the global bindings. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: use a dynamic array for global bindingsChia-I Wu2014-11-062-32/+70
| | | | | | | Use util_dynarray in ilo_set_global_binding() to allow for unlimited number of global bindings. Add a comment for global bindings. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add kernel queries for compute shadersChia-I Wu2014-11-063-0/+37
| | | | | | | We need to know the local/input/private sizes and others. This is not complete. We need many others for CURBE setup. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: fix compute paramsChia-I Wu2014-11-061-12/+36
| | | | | | Based on beignet, hardware capabilities, and OpenCL requirements. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: add eu_count and thread_count to ilo_dev_infoChia-I Wu2014-11-063-55/+77
| | | | | | | They will be used to report compute params or program compute states. thread_count can also be used for 3DSTATE_VS. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: fix intel_bo_wait() on kernel 3.17Chia-I Wu2014-11-061-1/+7
| | | | | | drm_intel_gem_bo_wait() with negative timeout is broken on kernel 3.17. Signed-off-by: Chia-I Wu <[email protected]>
* mesa: Silence unused parameter warning in check_context_limits in non-debug ↵Ian Romanick2014-11-051-0/+2
| | | | | | | | | | builds ../../src/mesa/main/context.c: In function 'check_context_limits': ../../src/mesa/main/context.c:733:41: warning: unused parameter 'ctx' [-Wunused-parameter] Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util: Implement unreachable for MSVC using __assumeIan Romanick2014-11-051-0/+6
| | | | | | | | | Based on the description of __assume at: http://msdn.microsoft.com/en-us/library/1b3fsfxw.aspx Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Fix sampler state pointer adjustment for nonconst samplersChris Forbes2014-11-051-1/+1
| | | | | | | | | | | This started hitting an assertion recently. Only affects Haswell (Ivybridge doesn't support this meddling with the sampler state pointer, and ARB_gpu_shader5 is not enabled yet on Broadwell) 14 Piglits crash->pass. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ilo: add drm_configuration for the pipe-targetNick Sarnie2014-11-041-1/+22
| | | | Allows the driver to advertise DMA-BUF and throttling.
* i965: Re-enable Z16 on Gen8+.Kenneth Graunke2014-11-041-0/+7
| | | | | | | | | | | | | Improves performance in GLBenchmark 2.7 TRex by 3.88889% +/- 0.336383% (n=80) at 1280x720 on Broadwell GT3. Together with the previous patch, it improves performance by 5.42738% +/- 0.541971% (n=10) at 1920x1080. Note that without the PMA stall fix, this would instead decrease performance by 22%. v2: Update comment (noticed by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-044-0/+180
| | | | | | | | | | | | | | | | | | | Certain non-promoted depth cases typically incur stalls. In very specific cases, we can enable a workaround which improves performance. Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765% (n=75) at 1280x720 on Broadwell GT3. Haswell has this feature as well, but we can't currently write registers from userspace batches (and we'd incur additional software batch scanning overhead as well), so we haven't enabled it. Broadwell allows us to write CACHE_MODE_1. Backporters beware: the formula and flushing incantation differs between Haswell and Broadwell. v2: Move pma_stall_bits from brw->state to brw itself (requested by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add #defines for Broadwell HiZ workarounds in CACHE_MODE_1.Kenneth Graunke2014-11-041-0/+6
| | | | | | This patch adds macros needed for the HiZ PMA stall optimization. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update compaction code to handle Skylake like Cherryview.Kenneth Graunke2014-11-031-4/+4
| | | | | | | | | Matt requested this in review feedback on the original patch, which I completely missed when pushing this series. Kristian also made this change, but I grabbed the wrong version of the patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Don't call _mesa_ClipControl from glPopAttrib when unsupported.Kenneth Graunke2014-11-031-1/+2
| | | | | | | Otherwise, calling glPopAttrib on drivers that don't support ARB_clip_control gives you a GL error, which is surprising at best. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Disable fast color clears on Skylake for now.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | We're not programming the clear values yet, so this won't work. This patch should be (effectively) reverted eventually. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-036-17/+33
| | | | | | | | | | | | On Skylake, the MOCS bits are an index into a table of 63 different, configurable cache configurations. As for previous GENs, we only care about WB and WT, which are available in the documented default set. Define SKL_MOCS_WB and SKL_MOCS_WT to the indices for those configucations and use those for the Skylake MOCS values. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Implement workaround for VF Invalidate issueJordan Justen2014-11-031-0/+9
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke2014-11-032-2/+10
| | | | | | | | | Skylake has separate controls for enabling the Z Clip Test for the near and far planes. For now, maintain the legacy behavior by setting both. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in 3DSTATE_DS on Skylake.Kenneth Graunke2014-11-031-10/+5
| | | | | | | | | Skylake's 3DSTATE_DS packet has a few more fields; we don't support domain shaders yet though. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Init instructions compaction tables for SKLKristian Høgsberg2014-11-031-0/+1
| | | | | | | They are the same as for BDW, so just add a case for SKL to the init switch. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Add fast clear resolve rect multipliers for SKLKristian Høgsberg2014-11-031-2/+5
| | | | | | | | SKL updates the resolve rectangle scaling factors again. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Always emit 3DSTATE_BINDING_TABLE_POINTERS_* on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | On SKL, 3DSTATE_CONSTANT_* command is not committed until we give the corresponding 3DSTATE_BINDING_TABLE_POINTERS_* command. If we fail to do so, the constant buffers wont be read and push constants will be wrong. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Allocate 16 DWords for SURFACE_STATE on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | Otherwise they overlap and horrible things happen. All the new DWords are for fast color clear values, which we don't do yet. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Refactor surface state allocation.Kenneth Graunke2014-11-031-10/+16
| | | | | | | | | | We will need to allocate more DWords on Skylake. v2: Don't mark brw_context parameter const. It's modified. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake.Kenneth Graunke2014-11-031-2/+11
| | | | | | | | | Skylake introduces a new base address for a feature we don't yet expose. Setting these to 0 should be safe. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke2014-11-033-6/+28
| | | | | | | | | Skylake uploads the stencil reference values in DW3 of the 3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | Skylake has some extra bits in PIPELINE_SELECT, none of which are interesting for a 3D driver. In order to selectively change them, it also introduces new "mask bits" in 15:8. We care about the "Pipeline Selection" bits (1:0), so set the mask to 0x3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Set max OpenGL version the same as gen7/8Jordan Justen2014-11-031-0/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update 3DSTATE_SBE for Skylake.Damien Lespiau2014-11-032-2/+34
| | | | | | | | | | | | | This commands has seen the addition of 2 dwords that allow to specify which channels of which attributes need to be forwarded to the fragment shader. v2: Rebase forward a year (done by Ken). Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* glsl: Improve the CSE pass debugging output.Kenneth Graunke2014-11-031-1/+8
| | | | | | | | The CSE pass now prints out why it thinks a value is not a candidate for adding to the AE set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't compute_to_mrf() on Gen >= 7.Matt Turner2014-11-031-0/+4
| | | | | | No differences in shader-db on Haswell (Gen 7.5). Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Remove now useless dot optimization on basis vectMatt Turner2014-11-033-92/+3
| | | | | | | The optimization in commit d056863b covers these cases, which were the first optimizations I added to the GLSL compiler. Reviewed-by: Ian Romanick <[email protected]>
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