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* r300: move some more function to genericDave Airlie2009-01-159-215/+217
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* radeon/r200/r300: start to make cmd buf usefulDave Airlie2009-01-159-105/+126
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* r100/r200: move to new atom style emissionDave Airlie2009-01-154-24/+40
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* radeon: get ctx right in copybufferDave Airlie2009-01-141-4/+2
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* r200: add missing symbolsDave Airlie2009-01-142-3/+1
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* radeon/r200/r300: make legacy emit non-r300 specificDave Airlie2009-01-147-33/+61
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* radeon: move debug symbol add DRI2Dave Airlie2009-01-145-13/+14
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* r300: start moving new r300 cmdbuf into common codeDave Airlie2009-01-1418-225/+194
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* radeon/r200/r300: consolidate swap buffersDave Airlie2009-01-1412-192/+80
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* radeon: remove old lock codeDave Airlie2009-01-143-369/+0
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* radeon/r200/r300: consolidate the buffer copy/flip code into one placeDave Airlie2009-01-1413-944/+404
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* radeon/r200/r300: attempt to move lock to common codeDave Airlie2009-01-1436-741/+738
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* radeon/r200/r300: initial attempt to convert to common context codeDave Airlie2009-01-1446-1226/+1067
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* radeon/r200: move more stuff closer together in contextDave Airlie2009-01-1412-117/+112
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* radeon/r200: move state atom to common headerDave Airlie2009-01-149-137/+103
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* radeon/r200: start splitting out commonalities into separate headersDave Airlie2009-01-1321-425/+279
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* radeon: use bo_wait to wait for all buffers to be rendered toDave Airlie2009-01-131-1/+10
| | | | | Not 100% sure this is correct, but its what Intel does and its better than CP_IDLE.
* Bump dri2proto requirement to 1.99.3, drop CopyRegion bitmask from protocol.Kristian Høgsberg2009-01-112-2/+1
| | | | (cherry picked from commit 154a9e5317f890618932cea0129ef887e16baf84)
* radeon/r300: add code to setup r300 vs r500 using pci device from kernelDave Airlie2009-01-111-149/+177
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* r300: disable settexoffset extension on r300Dave Airlie2008-12-221-1/+1
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* radeon: fix library name for consistencyDave Airlie2008-12-221-1/+1
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* radeon: remove start/end offset + cleanup some whitespaceDave Airlie2008-12-225-62/+33
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* radeon: fixup r500 FP emission for new CSDave Airlie2008-12-223-42/+95
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* radeno: hopefully make r200/radeon buildDave Airlie2008-12-212-4/+6
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* radeon: make DRI1 one work with new CS mechanismDave Airlie2008-12-0110-110/+187
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* radeon: cs add print cs callbackJerome Glisse2008-11-161-1/+6
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* radeon: fix pointer danglingJerome Glisse2008-11-166-12/+16
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* radeon: update to libdrm-radeon API changesJerome Glisse2008-11-156-21/+23
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* radeon: dri2 don't forget to free bufferJerome Glisse2008-11-143-1/+77
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* r300: release bo from pixmapJerome Glisse2008-11-143-4/+26
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* r300: convert to new relocations format (see libdrm-radeon)Jerome Glisse2008-11-147-49/+105
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* r300: SetTex extension supportJerome Glisse2008-11-149-19/+113
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* r300: cs + DRI2 supportJerome Glisse2008-11-1421-348/+958
| | | | | If DRI2 is enabled then switch cmd assembly to directly build hw packet.
* r300: bo and cs abstraction.Jerome Glisse2008-11-1436-3343/+3360
| | | | | | | | | | This abstract memory management and command stream building so we can use different backend either legacy one which use old pathway or a new one like with a new memory manager. This works was done by : Nicolai Haehnle Dave Airlie Jerome Glisse
* mesa: no longer need Writemask field in GLSL IR nodesBrian Paul2008-11-134-69/+23
| | | | The Swizzle and Size fields carry all the info we need now.
* mesa: revamp GLSL instruction emit codeBrian Paul2008-11-131-244/+381
| | | | | | | | | | | | | | | This is a step toward better array handling code. In particular, when more than one operand of an instruction uses indirect addressing, we'll need some temporary instructions and registers. By converting IR storage to instruction operands all in one place (emit_instruction()) we can be smarter about this. Also, somewhat better handling of dst register swizzle/writemask handling. This results in tighter writemasks on some instructions which is good for SOA execution. And, cleaner instruction commenting with inst_comment(). Next: remove some more dead code and additional clean-ups...
* mesa: make writemask_string() non-staticBrian Paul2008-11-132-4/+7
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* mesa: remove some do-nothing GLSL codeBrian Paul2008-11-131-16/+0
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* mesa: fix accidental regression in GLSL built-in texture matrix lookupBrian Paul2008-11-131-0/+1
| | | | Was broken by commit 9aca9a4b72b2a7b378e50bd88f9c3324d07375ec.
* mesa: use the tighter definition of GLSL ftransform() from the gallium branchesBrian Paul2008-11-132-31/+40
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* mesa: remove unused/obsolete __NormalMatrixTranspose matrixBrian Paul2008-11-133-188/+184
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* mesa: fix bug in GLSL built-in matrix state lookupBrian Paul2008-11-131-2/+5
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* mesa: tweak program register printing for RelAddr caseBrian Paul2008-11-131-1/+1
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* mesa: fix generation of fixed function state when no vp existsAlan Hourihane2008-11-131-43/+41
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* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
| | | | | This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
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* Add glsync demo program from jbarnes for testing vblank synchronization.Eric Anholt2008-11-123-0/+275
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* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
| | | | | | As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
| | | | | | We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
| | | | | | | | | The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
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