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* i965: Add script to gen code for OA counter queriesRobert Bragg2017-03-093-2/+575
* i965: extend query/counter structs for OA queriesRobert Bragg2017-03-092-1/+21
* i965: brw_context.h additions for OA unit query codegenRobert Bragg2017-03-091-0/+21
* i965: XML description of Haswell OA metric setRobert Bragg2017-03-091-0/+998
* nv50/ir: check for origin insn in findOriginForTestWithZeroPierre Moreau2017-03-091-0/+2
* mesa/main: make use of lookup_samplerobj_locked()Samuel Pitoiset2017-03-091-11/+1
* mesa/main: inline {begin,end}_samplerobj_lookups()Samuel Pitoiset2017-03-091-16/+2
* glsl/blob: clear padding bytesGrazvydas Ignotas2017-03-091-3/+6
* util/disk_cache: fix size subtraction on 32bitGrazvydas Ignotas2017-03-091-3/+3
* util/disk_cache: fix compressed size calculationGrazvydas Ignotas2017-03-091-1/+1
* glsl: builtin: always return clones of the builtinsLionel Landwerlin2017-03-093-8/+20
* i965: Delete render ring prelude.Kenneth Graunke2017-03-082-10/+0
* swr: s/uint/enum pipe_render_cond_flag/Vinson Lee2017-03-081-1/+1
* radv: Don't flush the CB before doing a fast clear eliminate.Bas Nieuwenhuizen2017-03-091-2/+0
* radv: Don't emit cache flushes on subpass switch.Bas Nieuwenhuizen2017-03-093-6/+0
* radv: Only flush for the needed stages, and before the flushes.Bas Nieuwenhuizen2017-03-091-6/+1
* radv: Don't invalidate CB/DB for images that aren't modified outside CB/DB.Bas Nieuwenhuizen2017-03-091-9/+19
* radv: Flush more caches after writes.Bas Nieuwenhuizen2017-03-091-3/+9
* radv: Don't flush for fixed-function reading.Bas Nieuwenhuizen2017-03-091-1/+0
* radv: Invalidate the correct caches for CB/DB dst barriers.Bas Nieuwenhuizen2017-03-091-5/+11
* radv: Determine cache flushes per object.Bas Nieuwenhuizen2017-03-091-17/+19
* mesa/main: remove unused _mesa_new_texture_image()Samuel Pitoiset2017-03-092-20/+0
* radv/ac: fixup texture coord to have right number of channels.Dave Airlie2017-03-092-4/+4
* st/nine: pass NULL to ureg_get_tokens()Timothy Arceri2017-03-092-4/+2
* docs: ARB_shader_atomic_counter_ops is enabled on i965/gen7+.Matt Turner2017-03-081-1/+1
* vc4: Fix math with a condition flag set.Eric Anholt2017-03-082-3/+18
* vc4: Fix register pressure cost estimates when a src appears twice.Eric Anholt2017-03-081-3/+13
* vc4: Report to shader-db how many threads a fragment shader has.Eric Anholt2017-03-081-0/+7
* Revert "vc4: Lazily emit our FS/VS input loads."Eric Anholt2017-03-084-93/+75
* radeonsi: fix elimination of literal VS outputsMarek Olšák2017-03-081-4/+7
* loader: Move non-error message to debug levelFabio Estevam2017-03-081-1/+1
* android: r600: fix libmesa_amd_common dependencyMauro Rossi2017-03-081-0/+1
* gallium/targets: rework the empty targets removalEmil Velikov2017-03-083-6/+3
* util/indices: minor clean-upsBrian Paul2017-03-082-5/+2
* radeonsi: s/uint/enum pipe_shader_type/Brian Paul2017-03-082-2/+4
* gallium: s/uint/enum pipe_render_cond_flag/ for set_render_condition()Brian Paul2017-03-0817-17/+19
* gallium: s/uint/enum pipe_shader_type/ for set_constant_buffer()Brian Paul2017-03-0820-20/+27
* gallium: s/unsigned/enum pipe_shader_type/ for get_compiler_options()Brian Paul2017-03-083-3/+5
* virgl: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-081-3/+3
* swr: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-084-6/+7
* softpipe: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-084-4/+6
* llvmpipe: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-081-1/+1
* freedreno: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-081-1/+1
* etnaviv: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-081-2/+2
* draw: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-084-14/+15
* cso: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-082-10/+12
* gallium: s/unsigned/enum pipe_shader_type/ for pipe_screen::get_shader_param()Brian Paul2017-03-0823-29/+62
* anv: change BLOCK_POOL_MEMFD_SIZE to exactly 2GBTapani Pälli2017-03-081-1/+1
* Revert "configure.ac: Use PKG_CHECK_VAR for wayland-scanner."Matt Turner2017-03-071-1/+6
* Revert "configure.ac: Use PKG_CHECK_VAR for libclc."Matt Turner2017-03-071-2/+4
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