summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* r600: don't emit atomic save if we have no atomic counters.Dave Airlie2017-11-141-0/+3
| | | | | | | Otherwise we end up emitting the fence. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glx/dri3: Fix passing renderType into glXCreateContextAdam Jackson2017-11-131-1/+2
| | | | | | | | | | Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig. Cc: [email protected] Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)Adam Jackson2017-11-131-4/+2
| | | | | | | | | | | This is perfectly legal in GL 3.0+. Fixes piglit/glx-create-context-current-no-framebuffer. Cc: [email protected] Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx: Lower GLX opcode lookup into SendMakeCurrentRequestAdam Jackson2017-11-131-9/+7
| | | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* aubinator: Don't skip the first field in each subgroupJason Ekstrand2017-11-131-2/+3
| | | | | | | | | | The previous iteration algorithm would advance the field pointer right after we advance the group. This meant that you would end up with skipping the first field of the group. In the common case, where the only field is a struct (e.g. 3DSTATE_VERTEX_BUFFERS), it would get skipped entirely. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Delete empty groupsJason Ekstrand2017-11-134-8/+0
| | | | | | | | | They serve no purpose other than to just fill empty space in the packet so each dword has something. Just disallowing empty groups is a bit easier on some of the tools. This does not change the generated packing headers in any way. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Don't crash on invalid heap sizes when the PCI ID is overridenJason Ekstrand2017-11-131-0/+12
|
* nir/spirv: tg4 requires a samplerAlex Smith2017-11-132-2/+1
| | | | | | | | | | Gather operations in both GLSL and SPIR-V require a sampler. Fixes gathers returning garbage when using separate texture/samplers (on AMD, was using an invalid sampler descriptor). Signed-off-by: Alex Smith <[email protected]> Cc: "17.2 17.3" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Use correct type for sampled imagesAlex Smith2017-11-133-6/+6
| | | | | | | | | | | | | | | | | | | | | | We should use the result type of the OpSampledImage opcode, rather than the type of the underlying image/samplers. This resolves an issue when using separate images and shadow samplers with glslang. Example: layout (...) uniform samplerShadow s0; layout (...) uniform texture2D res0; ... float result = textureLod(sampler2DShadow(res0, s0), uv, 0); For this, for the combined OpSampledImage, the type of the base image was being used (which does not have the Depth flag set, whereas the result type does), therefore it was not being recognised as a shadow sampler. This led to the wrong LLVM intrinsics being emitted by RADV. Signed-off-by: Alex Smith <[email protected]> Cc: "17.2 17.3" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add DO NOT EDIT warning on generated spirv_info.cAlejandro Piñeiro2017-11-131-1/+4
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* loader/dri3: Improve dri3 thread-safetyThomas Hellstrom2017-11-132-18/+69
| | | | | | | | | | | | | | | | | | | | | | | | | It turned out that with recent changes that call into dri3 from glFinish(), it appears like different thread end up waiting for X events simultaneously, causing deadlocks since they steal events from eachoter and update the dri3 counters behind eachothers backs. This patch intends to improve on that. It allows at most one thread at a time to wait on events for a single drawable. If another thread intends to do the same, it's put to sleep until the first thread finishes waiting, and then it rechecks counters and optionally retries the waiting. Threads that poll for X events never pulls X events off the event queue if there are other threads waiting for events on that drawable. Counters in the dri3 drawable structure are protected by a mutex. Finally, the mutex we introduce is never held while waiting for the X server to avoid unnecessary stalls. This does not make dri3 drawables completely thread-safe but at least it's a first step. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102358 Fixes: d5ba75f8881 "st/dri2 Plumb the flush_swapbuffer functionality through to dri3" Signed-off-by: Thomas Hellstrom <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* etnaviv: automake,meson: include common_3d.xml.h in the sources listsJuan A. Suarez Romero2017-11-132-0/+2
| | | | | | | v2: include the file also in the meson.build (Eric Engestrom). Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Reviewed-by: Eric Engestrom <[email protected]>
* egl: EXT_pixel_format_float plumbingTapani Pälli2017-11-135-0/+15
| | | | | | | | | | | | | | | Patch adds support and capability to match with new surface attribute, component type. Currently no configs with floating point type are exposed. With this change, following dEQP test starts to pass: dEQP-EGL.functional.choose_config.color_component_type_ext.dont_care dEQP-EGL.functional.choose_config.color_component_type_ext.fixed dEQP-EGL.functional.choose_config.color_component_type_ext.float Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* radv: add unlikely() around radv_save_descriptors()Samuel Pitoiset2017-11-131-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: optimize calling radv_cmd_buffer_trace_emit()Samuel Pitoiset2017-11-133-8/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: optimize calling radv_save_pipeline()Samuel Pitoiset2017-11-131-5/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use vk_zalloc instead of vk_alloc+memsetSamuel Pitoiset2017-11-134-21/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unnecessary memset() in radv_AllocateCommandBuffers()Samuel Pitoiset2017-11-131-3/+0
| | | | | | | | This should not be needed, if the allocation fails an error is returned and the host should handle it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless initializations in radv_create_cmd_buffer()Samuel Pitoiset2017-11-131-2/+0
| | | | | | | There is a memset() above. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove useless memset() in radv_CreateFence()Samuel Pitoiset2017-11-131-1/+0
| | | | | | | All radv_fence fields are initialized here. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use vk_error() everywhere an error is returnedSamuel Pitoiset2017-11-138-27/+27
| | | | | | | For consistency and it might help for debugging purposes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make radv_emit_framebuffer_state() staticSamuel Pitoiset2017-11-132-3/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit the framebuffer when restoring a passSamuel Pitoiset2017-11-131-1/+1
| | | | | | | | Instead just dirty RADV_CMD_DIRTY_FRAMEBUFFER and it will be re-emitted if necessary before the next draw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: prefetch VBO descriptors at the right placeSamuel Pitoiset2017-11-132-0/+21
| | | | | | | | | | | Just after the vertex shader. This seems to give a minor boost for, at least, Serious Sam Fusion 2017 and Dawn of War 3. I don't see any real impacts with The Talos Principle. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_emit_prefetch_TC_L2_async() helperSamuel Pitoiset2017-11-131-2/+9
| | | | | | | Will be used for VBO descriptors prefetching. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_emit_shaders_prefetch() to radv_emit_prefetch()Samuel Pitoiset2017-11-131-6/+6
| | | | | | | | For consistency because this function will also prefetch VBO descriptors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/linker: use without_array() to retrieve typeIago Toral Quiroga2017-11-131-3/+4
| | | | | | | | This is what we do in the condition too, so it makes sense. v2: Only compute without_array() once (Ilia). Reviewed-by: Ilia Mirkin <[email protected]>
* radv: emit esgs ring size in one place.Dave Airlie2017-11-132-7/+8
| | | | | | | | | This register is the same on all gpus so far, so emit it in one place and also for the pre-gfx9 gpus set the value in the pipeline creation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating vs out info regs into pipeline.Dave Airlie2017-11-133-25/+34
| | | | | | | | This moves some calculations of register values into the pipeline construction, it saves looking at outinfo in the cmd buffer emit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a5xx: fix SSBO emit for non-zero offsetRob Clark2017-11-121-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove obsolete commentRob Clark2017-11-121-4/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't create split/fo if only writing .xRob Clark2017-11-121-0/+6
| | | | | | | In case an instruction only writes one register, and it is .x, we can skip the extra level of fanout indirection. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect gridsRob Clark2017-11-123-20/+86
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add global size compute capRob Clark2017-11-121-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: turn on std430 packingRob Clark2017-11-121-1/+6
| | | | | | Seems to fix dEQP compute related tests.. and matches what i965 does, so perhaps there is some assumption that std430 packing is on by default somewhere in NIR?
* freedreno/a5xx: image supportRob Clark2017-11-128-31/+306
|
* freedreno/ir3: moar better schedulerRob Clark2017-11-125-58/+227
| | | | | | | | | | | | | | | | | | Add a new pass that inserts additional dependencies, rather than simply relying on SSA srcs added in the nir->ir3 frontend. This makes it easier to deal with barriers, but the additional false deps also lets us deal properly with ensuring a write depends on all previous reads. Since conversion to barrier instructions is lossy (ie. just knowing the instruction doesn't tell us enough about what other instructions the barrier applies to), use barrier_class/barrier_conflict fields in the ir3_instruction to retain this information. This could probably be relaxed somewhat by considering *which* array/ buffer/image variable is being referenced. Ie. a write to buffer A can overtake a read from buffer B, if B is not coherent. (right?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move macrosRob Clark2017-11-121-15/+15
| | | | | | | | | | I want to add a growable array to ir3_instruction, so we can append false dependencies for purposes of scheduling barriers, atomics, and dealing with write after read hazards. Just code motion preparing for next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image supportRob Clark2017-11-125-0/+337
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shared variable supportRob Clark2017-11-123-2/+177
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some SSBO cleanups/fixesRob Clark2017-11-122-15/+39
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out INSTR4F instructionsRob Clark2017-11-122-29/+64
| | | | | | | | Atomic instructions take a different # of src args depending on .g or .l variant, split these out into different helpers with INSTR*F() helper macro that lets you specify instruction flag. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cat6 encoding fixesRob Clark2017-11-124-32/+151
| | | | | | | Instruction encoding/decoding fixes needed for images, shared variables, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add barriersRob Clark2017-11-122-0/+55
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: invert is_same_type_mov() logicRob Clark2017-11-121-10/+16
| | | | | | | | Some instructions (like barriers) have no dst, which causes problems with dereferencing a NULL dst. Flip the logic around to reject opc's that can't be a type of move first, to filter out those instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add cat7 instructionsRob Clark2017-11-124-2/+79
| | | | | | Needed for memory and execution barriers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add SSBO get_buffer_size() supportRob Clark2017-11-126-11/+122
| | | | | | Somehow I overlooked this when adding initial SSBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: extract helper for common constsRob Clark2017-11-121-34/+17
| | | | | | | | User consts and driver consts such as UBO addresses and immediates are handled the same for all shader stages, so split out a shared helper for these, to make it easier to add more. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add image view state trackingRob Clark2017-11-122-0/+56
| | | | | | | | | It is unfortunate that image state isn't a real CSO, since (at least for a4xx/a5xx) it is a combination of sampler and "SSBO" image state, and it would be useful to pre-compute the state block "register" values rather than doing it at emit time. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-126-19/+142
| | | | Signed-off-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 14:16:55 +0000