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* i965: Don't grow batch/state buffer on every emit after an overflow.Kenneth Graunke2017-11-291-23/+19
| | | | | | | | | | | | | | | | | | | | Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we try and flush. If we're not allowed to flush, we resort to growing the buffer so that there's space for the data we need to emit. We accidentally got the threshold wrong. The first non-wrappable call beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ), The next call would see we were beyond STATE_SZ and think we needed to grow a second time - when the buffer was already large enough. We still want to flush when we hit STATE_SZ, but for growing, we should use the actual size of the buffer as the threshold. This way, we only grow when actually necessary. v2: Simplify the control flow (suggested by Jordan) Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Reviewed-by: Jordan Justen <[email protected]>
* i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.Kenneth Graunke2017-11-291-0/+3
| | | | | | | | | The original state buffer was marked with EXEC_OBJECT_CAPTURE. When growing it, we want to preserve that flag so we continue to capture it in GPU hang reports. Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Reviewed-by: Ian Romanick <[email protected]>
* i965: Use old_bo->align when growing batch/state buffer instead of 4096.Kenneth Graunke2017-11-291-1/+2
| | | | | | | | | | | | | | The intention here is make the new BO use the same alignment as the old BO. This isn't strictly necessary, but we would have to update the 'alignment' field in the validation list when swapping it out, and we don't bother today. The batch and state buffers use an alignment of 4096, so this should be equivalent - it's just clearer than cut and pasting a magic constant. Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* r600: no need to reinit compute regsDave Airlie2017-11-301-13/+0
| | | | | | | Compute setup gets emitted into the normal gfx state buffer, so no need to reinit the basics. Signed-off-by: Dave Airlie <[email protected]>
* r600: split cb setup code out from evergreen compute path.Dave Airlie2017-11-301-22/+28
| | | | | | This just makes it easier to bypass for TGSI later. Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for compute pkt flags to debug dumping.Dave Airlie2017-11-301-6/+7
| | | | | | This just lets us see packets marked for compute. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix bfe where src/dst are same.Dave Airlie2017-11-301-5/+24
| | | | | | | | This fixes overlaps where src/dst are the same. Fixes a bunch of the deqp bitfield tests. Signed-off-by: Dave Airlie <[email protected]>
* gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_controlAdam Jackson2017-11-291-0/+2
| | | | | Reviewed-and-tested-by: Nicolai Hähnle <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965: Program the dynamic state heap size to MAX_STATE_SIZE.Kenneth Graunke2017-11-293-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | STATE_BASE_ADDRESS specifies a maximum size of the dynamic state section, beyond which data supposedly reads back as 0. On Gen8+, we were programming it to the size of the buffer. This worked fine until we started growing the state buffer in commit 2dfc119f22f25708. When the state buffer grows, the value in STATE_BASE_ADDRESS becomes too small, and our state beyond STATE_SZ bytes would read back as 0. To avoid having to update the value, we program it to MAX_STATE_SIZE. We used to program the upper bound to the maximum on older hardware anyway, so programming it too large isn't a big deal. Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering. DiRT Rally was hitting the statebuffer growth path, and suffered from bad texture corruption and GPU hangs (usually around the same time). This patch fixes both issues. Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101 Tested-by: Jordan Justen <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*Marek Olšák2017-11-2929-57/+55
| | | | | | and handle PIPE_FLUSH_HINT_FINISH in r300. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_screenMarek Olšák2017-11-2940-873/+864
| | | | | | | | | | Most files in gallium/radeon now include si_pipe.h. chip_class and family are now here: sscreen->info.family sscreen->info.chip_class Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2Marek Olšák2017-11-293-8/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove query/apply_opaque_metadata callbacksMarek Olšák2017-11-293-114/+102
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move shader debug helpers out of r600_pipe_common.cMarek Olšák2017-11-297-26/+24
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: dismantle si_common_screen_init/destroyMarek Olšák2017-11-295-160/+154
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: document our vendor string situationMarek Olšák2017-11-291-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set all pipe buffer functions in r600_buffer_common.cMarek Olšák2017-11-294-45/+44
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/uvd: don't call ws->query_infoMarek Olšák2017-11-291-9/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move video queries into si_get.cMarek Olšák2017-11-294-168/+151
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove more functions from r600_pipe_common.cMarek Olšák2017-11-293-35/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move/remove ac_shader_binary helpersMarek Olšák2017-11-296-27/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.cMarek Olšák2017-11-296-852/+903
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove R600_CONTEXT_* flagsMarek Olšák2017-11-297-31/+27
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: just include si_pipe.h in r600_query.cMarek Olšák2017-11-293-7/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove some definitions and helpers from r600_pipe_common.hMarek Olšák2017-11-2913-136/+125
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use fast color clear for small surfacesMarek Olšák2017-11-291-0/+17
| | | | | | This removes 35+ clear eliminate passes from DOTA 2. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unify code setting dirty_level_mask for fast clearMarek Olšák2017-11-291-14/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up si_do_fast_color_clear parametersMarek Olšák2017-11-291-10/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_context::clear_bufferMarek Olšák2017-11-295-20/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move r600_test_dma.c into si_test_dma.cMarek Olšák2017-11-298-20/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move si_pipe_clear_buffer into si_cp_dma.cMarek Olšák2017-11-292-61/+61
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all clear() code into si_clear.cMarek Olšák2017-11-299-719/+764
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-295-2/+15
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement fast color clear for DCC with MSAA for VIMarek Olšák2017-11-291-5/+30
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for blending with DCC and MSAAMarek Olšák2017-11-291-8/+23
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe sideMarek Olšák2017-11-291-0/+10
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: enable DCC computation for MSAAMarek Olšák2017-11-293-6/+6
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix layered DCC fast clearMarek Olšák2017-11-291-1/+4
| | | | | Cc: 17.2 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* util: Also include endian.h on cygwinJon Turney2017-11-291-1/+1
| | | | | | | | If u_endian.h can't determine the endianess, the default behaviour in sha1.c is to build for big-endian Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: deal with vs_inputs as 64-bit unsigned integerJuan A. Suarez Romero2017-11-291-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer. But actually it is a 64-bit integer, and as such it is used in other parts of Mesa code. It is worth to note that bits from the entire range are used, and not only 32-bits. This is due our implementation for handling 64-bit dual-slot input attributes, which requires to use a larger bitfield to manage them. This commit reverts the changes done in brw_draw_upload.c, keeping the rest of the changes. This fixes the following tests: - KHR-GL45.enhanced_layouts.varying_array_locations - KHR-GL45.enhanced_layouts.varying_locations Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942 CC: Marek Olšák <[email protected]> CC: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]>
* mesa: rework _mesa_add_parameter() to only add a single paramTimothy Arceri2017-11-293-39/+41
| | | | | | | | | This is more inline with what the functions name suggests it should do, and makes the code much easier to follow. This will also make adding uniform packing support much simpler. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: lds load cleanups.Dave Airlie2017-11-291-6/+8
| | | | | | This is just some cleanups on top of the last patch from my compute branch. Signed-off-by: Dave Airlie <[email protected]>
* r600_shader: only load from LDS what is really usedGert Wollny2017-11-291-7/+26
| | | | | | | | Use the destination write mask to determine which values are really to be read from LDS and load only these. Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Gert Wollny <[email protected]>
* r600/sb: handle jump after target to end of program. (v2)Dave Airlie2017-11-291-0/+5
| | | | | | | | | | | | | | | | This fixes hangs on cayman with tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test This has a single if/else in it, and when this peephole activated, it would set the jump target to NULL if there was no instruction after the final POP. This adds a NOP if we get a jump in this case, and seems to fix the hangs, so we have a valid target for the ELSE instruction to go to, instead of 0 (which causes infinite loops). v2: update last_cf correctly. (I had some other patches hide this) Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Change a ret == -1 check to ret != 0.Kenneth Graunke2017-11-281-1/+1
| | | | | | For consistency with most other ret checks. Suggested by Chris. Reviewed-by: Chris Wilson <[email protected]>
* i965: Use C99 struct initializers in brw_bufmgr.c.Kenneth Graunke2017-11-281-91/+49
| | | | | | | | | | This is cleaner than using a non-standard memclear macro (which does a memset to 0) and then initializing fields after the fact. We move the declarations to where we initialized the fields. While we're at it, we move the declaration of 'ret' that goes with the ioctl, eliminating the declaration section altogether. Reviewed-by: Chris Wilson <[email protected]>
* i965: Move perf_debug and WARN_ONCE back to brw_context.h.Kenneth Graunke2017-11-282-29/+29
| | | | | | | | These were moved to src/intel/common/gen_debug.h, but they are not common code. They assume that brw_context or gl_context variables exist, named brw or ctx. That isn't remotely true outside of i965. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: const a few structs and vars to avoid writing to them by accidentEric Engestrom2017-11-281-4/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix Smooth Point Enables.Kenneth Graunke2017-11-281-1/+1
| | | | | | | | | | We want to program the 3DSTATE_RASTER field to the gl_context value, not the other way around. Fixes: 13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: build virgl driverDylan Baker2017-11-286-6/+114
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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