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* etnaviv: Don't flush on transfer when UNSYNCHRONIZEDWladimir J. van der Laan2017-11-021-12/+12
| | | | | | | | | Structure code to only flush when we will potentially call cpu_prep. This prevents spurious flushes in applications that heavily rely on u_uploader. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: don't do resolve-in-place without valid TSWladimir J. van der Laan2017-11-024-0/+11
| | | | | | | | | | | | GC3000 resolve-in-place assumes that the TS state is configured. If it is not, this will result in MMU errors. This is especially apparent when using glGenMipmaps(). Fixes: 78ade659569e ("etnaviv: Do GC3000 resolve-in-place when possible") Cc: [email protected] Signed-off-by: Wladimir J. van der Laan <[email protected]> Tested-by: Chris Healy <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* radv: make radv_bind_descriptor_set() staticSamuel Pitoiset2017-11-022-6/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make sure we set buffers as shareable properly.Dave Airlie2017-11-022-2/+7
| | | | | | | | | | | This should make sure we don't treat exports buffers as local bos. Fixes: a639d40f13 (radv: add support for local bos. (v3)) Tested-by: Andres Rodriguez <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: Use __asm__ instead of asmDylan Baker2017-11-013-11/+5
| | | | | | | | | | | | __asm__ is portable, and allows the svga driver to be compiled with the c99 standard instead of requiring the gnu99 standard. I have compile tested this with GCC and Clang on Linux. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."Marek Olšák2017-11-017-16/+1
| | | | | | This reverts commit f03b7c9ad92c1656a221297819fbc6d065cc0af7. The libdrm interface is wrong.
* intel: decoder: enable decoding a single fieldLionel Landwerlin2017-11-012-0/+52
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: expose missing find_enum()Lionel Landwerlin2017-11-011-0/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: extract field value computationLionel Landwerlin2017-11-011-30/+37
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: rename field() to field_value()Lionel Landwerlin2017-11-011-18/+18
| | | | | | | We would like to avoid collisions with variables named field. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: rename internal function to free nameLionel Landwerlin2017-11-011-3/+3
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: simplify field_is_header()Lionel Landwerlin2017-11-012-4/+6
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: common: make intel utils available from C++Lionel Landwerlin2017-11-013-0/+25
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: remove unused platform fieldLionel Landwerlin2017-11-011-2/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: error-decode: implement a rolling window of programsLionel Landwerlin2017-11-011-14/+23
| | | | | | | | | | | | | | If we have more programs than what we can store, aubinator_error_decode will assert. Instead let's have a rolling window of programs. v2: Fix overflowing issues (Eric Engestrom) v3: Go through programs starting at idx_program (Scott) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* gallium: increase pipe_sampler_view::target bitfield size for MSVCBrian Paul2017-11-011-2/+6
| | | | | | | | | | | | | | | | | | MSVC treats enums as being signed. The 4-bit target field isn't large enough to correctly store the value 8 (for PIPE_TEXTURE_CUBE_ARRAY). The bitfield value 0x8 was being interpreted as -8 so matching the target with PIPE_TEXTURE_CUBE_ARRAY in switch statements, etc. was failing. To keep the structure size the same, we reduce the format field from 16 bits to 15. There don't appear to be any other enum bitfields which need to be adjusted. This fixes a number of Piglit cube map array tests. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* mapi: fix .so path in ABI-checkEric Engestrom2017-11-012-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* intel: decoder: extract instruction/structs lengthLionel Landwerlin2017-11-012-0/+8
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: pack iterator variable declarationsLionel Landwerlin2017-11-011-11/+8
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: simplify creation of struct when 0-allocatedLionel Landwerlin2017-11-011-4/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: add destructor for gen_specLionel Landwerlin2017-11-012-102/+91
| | | | | | | | This makes use of ralloc to simplify the destruction. We can also store instructions in hash tables. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: expose helper to test header fieldsLionel Landwerlin2017-11-012-3/+4
| | | | | | | | These fields are of little importance as they're used to recognize instructions. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: don't read qword outside instruction/struct limitLionel Landwerlin2017-11-012-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used to print invalid data when the last field was being clamped to 32bits due to Dword Length of the whole instruction. Here is an example where the decoder read part of the next instruction instead of stopping at the 32bit limit: 0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM 0x000ce0b4: 0x10000002 : Dword 0 DWord Length: 2 Store Qword: 0 Use Global GTT: false 0x000ce0b8: 0x00045010 : Dword 1 Core Mode Enable: 0 Address: 0x00045010 0x000ce0bc: 0x00000000 : Dword 2 0x000ce0c0: 0x00000000 : Dword 3 Immediate Data: 8791026489807077376 With this change we have the proper value : 0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM (4 Dwords) 0x000ce0b4: 0x10000002 : Dword 0 DWord Length: 2 Store Qword: 0 Use Global GTT: false 0x000ce0b8: 0x00045010 : Dword 1 Core Mode Enable: 0 Address: 0x00045010 0x000ce0bc: 0x00000000 : Dword 2 0x000ce0c0: 0x00000000 : Dword 3 Immediate Data: 0 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: split out getting the next field and decoding itLionel Landwerlin2017-11-011-10/+21
| | | | | | | | | Due to the new way we handle fields, we need *not* to forget the first field when decoding instructions. The issue was that the advance function was called first and skipped the first field. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: move field name copyLionel Landwerlin2017-11-011-2/+7
| | | | | | | This should be inside the function that actually decodes fields. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: reorder iterator init functionLionel Landwerlin2017-11-011-14/+14
| | | | | | | Making the next change more readable. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: common: print out all dword with field spanning multiple dwordsLionel Landwerlin2017-11-011-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For example, we were skipping Dword 3 in this PIPE_CONTROL : 0x000ce130: 0x7a000004: PIPE_CONTROL DWord Length: 4 0x000ce134: 0x00000010 : Dword 1 Flush LLC: false Destination Address Type: 0 (PPGTT) LRI Post Sync Operation: 0 (No LRI Operation) Store Data Index: 0 Command Streamer Stall Enable: false Global Snapshot Count Reset: false TLB Invalidate: false Generic Media State Clear: false Post Sync Operation: 0 (No Write) Depth Stall Enable: false Render Target Cache Flush Enable: false Instruction Cache Invalidate Enable: false Texture Cache Invalidation Enable: false Indirect State Pointers Disable: false Notify Enable: false Pipe Control Flush Enable: false DC Flush Enable: false VF Cache Invalidation Enable: true Constant Cache Invalidation Enable: false State Cache Invalidation Enable: false Stall At Pixel Scoreboard: false Depth Cache Flush Enable: false 0x000ce138: 0x00000000 : Dword 2 Address: 0x00000000 0x000ce140: 0x00000000 : Dword 4 Immediate Data: 0 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: decoder: build sorted linked lists of fieldsLionel Landwerlin2017-11-012-25/+34
| | | | | | | | | | The xml files don't always have fields in order. This might confuse our parsing of the commands. Let's have the fields in order. To do this, the easiest way it to use a linked list. It also helps a bit with the iterator. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel: common: expose gen_spec fieldsLionel Landwerlin2017-11-012-13/+13
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* travis: build meson first for quicker feedbackEric Engestrom2017-11-011-32/+32
| | | | | | | | | | | Meson is much quicker to build Mesa, giving quicker feedback if executed first. Cc: Dylan Baker <[email protected]> Cc: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* meson: bump libdrm version required by amdgpuEric Engestrom2017-11-011-1/+1
| | | | | | | | Fixes: f03b7c9ad92c1656a221 "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx." Cc: Andrey Grodzovsky <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is falseJordan Justen2017-10-314-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | (Apologies for the double negative.) For now, the shader cache is disabled by default on i965 to allow us to verify its stability. In other words, to enable the shader cache on i965, set MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then the shader cache will be disabled. We use the build-id of i965_dri.so for the timestamp, and the pci device id for the device name. v2: * Simplify code by forcing link to include build id sha. (Matt) v3: * Don't use a for loop with snprintf for bin to hex. (Matt) * Assume fixed length render and timestamp string to further simplify code. Cc: Matt Turner <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri drivers: Always add the sha1 build-idJordan Justen2017-10-315-1/+5
| | | | | | | | | | | v4: * Add Android build changes. (Emil) Cc: Dylan Baker <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* disk_cache: Fix issue reading GLSL metadataJordan Justen2017-10-311-1/+1
| | | | | | | | | | | | | | This would cause the read of the metadata content to fail, which would prevent the linking from being skipped. Seen on Rocket League with i965 shader cache. Fixes: b86ecea3446e "util/disk_cache: write cache item metadata to disk" Cc: Timothy Arceri <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl/shader_cache: Save fs (BlendSupport) metadataJordan Justen2017-10-311-0/+6
| | | | | | | | | | | | | | | | | | Fixes many GL 4.5 CTS blend tests, such as: * GL45-CTS.blend_equation_advanced.extension_directive_enable * GL45-CTS.blend_equation_advanced.extension_directive_warn * GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier * GL45-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR v2: * Directly save the BlendSupport field to avoid potentially including a pointer in the future in the structure is updated. (tarceri) Cc: Timothy Arceri <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Initialize sha1 hash of dri config optionsJordan Justen2017-10-311-0/+4
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't link when the program was found in the disk cacheJordan Justen2017-10-311-0/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Cc: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add cache fallback support using serialized nirJordan Justen2017-10-311-1/+26
| | | | | | | | | | | | | | | | If the i965 gen program cannot be loaded from the cache, then we fallback to using a serialized nir program. This is based on "i965: add cache fallback support" by Timothy Arceri <[email protected]>. Tim's version was written to fallback to compiling from source, and therefore had to be much more complex. After Connor and Jason implemented nir serialization, I was able to rewrite and greatly simplify this patch. Signed-off-by: Jordan Justen <[email protected]> Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add support for cached shaders with xfb qualifiersTimothy Arceri2017-10-311-0/+8
| | | | | | | | | | For now this disables the shader cache when transform feedback is enabled via the GL API as we don't currently allow for it when generating the sha for the shader. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/glsl: add api_enabled flag to gl_transform_feedback_infoTimothy Arceri2017-10-312-1/+7
| | | | | | | | | | This will be used to disable the shader cache when xfb is enabled via the api as we don't currently allow for it when generating the sha for the shader. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add shader cache support for computeJordan Justen2017-10-315-12/+53
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add shader cache support for tess stagesTimothy Arceri2017-10-313-16/+70
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add shader cache support for geometry shadersTimothy Arceri2017-10-312-8/+35
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add shader cache support for vertex and fragment stagesTimothy Arceri2017-10-313-16/+30
| | | | | | | | | | | | | This enables the cache on vertex and fragment shaders only. v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: reword subject] [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add initial implementation of on disk shader cacheTimothy Arceri2017-10-314-0/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the Mesa disk_cache support to write out the final linked binary for vertex and fragment shader programs. This is based off the initial implementation done by Carl Worth. It has been significantly reworked, first by Tim Arceri, and then by Jordan Justen. v2: * Squash 'i965: add image param shader cache support' * Squash 'i965: add shader cache support for pull param pointers' * Sustantially simplified by a rework on top of Jason's 2975e4c56a7a. * Rename load_program_data to read_program_data. (Jason) v3: * Simplify and align program read/write. (Jason) v4: * Don't save prog_data size since we know it from the stage. (Ken) * Don't save program size, since prog_data includes the size. (Ken) * Remove `assert` that potentially could be triggered by disk corruption of the cache entries. (Ken) * Fix compute shader scratch allocation. (Ken) * Remove special case mapping for non-LLC. (Ken) * Remove SET_UPLOAD_PARAMS macro [[email protected]: *_cached_program => brw_disk_cache_*_program] [[email protected]: brw_shader_cache.c => brw_disk_cache.c] [[email protected]: don't map to write program when LLC is present] [[email protected]: set program_written_to_cache on read from cache] [[email protected]: only try cache when status is linking_skipped] [[email protected]: all v2-v4 changes noted above] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Calculate thread_count in brw_alloc_stage_scratchJordan Justen2017-10-318-45/+62
| | | | | | | | | | Previously, thread_count was sent in from the stage after some stage specific calculations. Those stage specific calculations were moved into brw_alloc_stage_scratch, which will allow the shader cache to also use the same calculations. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Add functions to get prog_data and prog_key sizes for a stageJordan Justen2017-10-312-0/+42
| | | | | | | | | v2: * Return unsigned instead of size_t. (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Add union types for prog_data and prog_key stagesJordan Justen2017-10-311-0/+22
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* blob: Don't set overrun if reading 0 bytes at end of dataJordan Justen2017-10-311-1/+1
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-3117-92/+55
| | | | | | | | | The caller can now use brw_stage_prog_data::program_size which is set by the brw_compile_* functions. Cc: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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