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* gallium/radeon: fix (S)DMA read-after-write hazardsMarek Olšák2016-05-108-0/+32
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: raise the max size for SDMA buffer copiesMarek Olšák2016-05-102-3/+3
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove SDMA texture copy codeMarek Olšák2016-05-101-215/+2
| | | | | | | | | Most of this has never worked according to the new test. The new code will be radically different. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: only expose *_init_*dma_functions from (S)DMA filesMarek Olšák2016-05-105-34/+31
| | | | | | | just normalizing the interfaces Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: implement randomized SDMA texture copy testing (v2)Marek Olšák2016-05-106-0/+419
| | | | | | | | | | | v2: - adjustments for exercising all important SDMA code paths - decrease the probability of getting huge sizes (faster testing) - increase the probability of getting power-of-two dimensions - change the memory cap to 128MB (faster testing) - better detect which engine has been used Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: discard CMASK or DCC if overwriting a whole texture by DMAMarek Olšák2016-05-101-7/+39
| | | | | | | v2: simplify the conditionals Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use a common function for DMA blit preparationMarek Olšák2016-05-106-31/+73
| | | | | | | this is more robust and probably fixes some bugs already Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: split out code for discarding DCCMarek Olšák2016-05-101-6/+12
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename r600_texture_disable_cmask -> discard_cmaskMarek Olšák2016-05-101-2/+2
| | | | | | | because it doesn't decompress Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use transfer_inline_write for memcpy TexSubImage pathMarek Olšák2016-05-101-4/+39
| | | | | | This allows drivers to use their own fast path for texture uploads. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix partial layered transfers of cube (array) texturesMarek Olšák2016-05-101-15/+6
| | | | | | | | | a staging cube texture with array_size % 6 != 0 doesn't work very well just use 2D_ARRAY or 2D for all staging textures Cc: 11.1 11.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: align alignments for better buffer reuseMarek Olšák2016-05-102-0/+2
| | | | | | | | It's for the buffer cache. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-106-10/+18
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: use gart_page_size instead of private size_alignMarek Olšák2016-05-103-14/+11
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-104-10/+10
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: print declarations of intrinsics with GALLIVM_DEBUG=irRoland Scheidegger2016-05-101-0/+5
| | | | | | | Those aren't really interesting, however outputting them is helpful when trying to feed the IR to llvm llc (or opt) for debugging. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: use InternalLinkage instead of PrivateLinkage for texture functionsRoland Scheidegger2016-05-101-1/+1
| | | | | | | At least with MCJIT the disassembler will crash otherwise when trying to disassemble such functions. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: disable avx512 featuresRoland Scheidegger2016-05-101-0/+12
| | | | | | | | | | | | | | | We don't target this yet, and some llvm versions incorrectly enable it based on cpu string, causing crashes. (Albeit this is a losing battle, it is pretty much guaranteed when the next new feature comes along llvm will mistakenly enable it on some future cpu, thus we would have to proactively disable all new features as llvm adds them.) This should fix https://bugs.freedesktop.org/show_bug.cgi?id=94291 (untested) Tested-by: Timo Aaltonen <[email protected]> Reviewed-by: Jose Fonseca <[email protected] CC: <[email protected]>
* Revert "nir: Try to warn when C99 extensions are used in nir headers."Jose Fonseca2016-05-101-22/+1
| | | | | | | | | | This reverts commit 99474dc29b0f45413d0e538d7321da9ad4c9f6f5. -Wpedantic is too verbose, even when applied to just a few includes. We'll just have to deal with the issues as they come. Reviewed-by: Brian Paul <[email protected]>
* i965/fs: fix MOV_INDIRECT exec_size for doublesSamuel Iglesias Gonsálvez2016-05-101-1/+9
| | | | | | | | | | | | | In that case, the writes need two times the size of a 32-bit value. We need to adjust the exec_size, so it is not breaking any hardware rule. v2: - Add an assert to verify type size is not less than 4 bytes (Jordan). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: take into account doubles when calculating read_size for MOV_INDIRECTSamuel Iglesias Gonsálvez2016-05-101-2/+3
| | | | | | | | | v2: - Fix assert's line width (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: demote_pull_constants() did not take into account double typesSamuel Iglesias Gonsálvez2016-05-101-1/+8
| | | | | | | | | | | The constants could be double, and it was allocating size for float types for the destination register of varying pull constant loads. Then the fs_visitor::validate() will complain. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: push first double-based uniforms in push constant bufferSamuel Iglesias Gonsálvez2016-05-101-30/+82
| | | | | | | | | | | | | | | | | | | | | When there is a mix of definitions of uniforms with 32-bit or 64-bit data type sizes, the driver ends up doing misaligned access to double based variables in the push constant buffer. To fix this, this patch pushes first all the 64-bit variables and then the rest. Then, all the variables would be aligned to its data type size. v2: - Fix typo and improve comment (Jordan). - Use ralloc(NULL,...) instead of rzalloc(mem_ctx,...) (Jordan). - Fix typo (Topi). - Use pointers instead of references in set_push_pull_constant_loc() (Topi). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: recognize writes with a subreg_offset > 0 as partialIago Toral Quiroga2016-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | Usually, writes to a subreg_offset > 0 would also have a stride > 1 and we would recognize them as partial, however, there is one case where this does not happen, that is when we generate code for 64-bit imemdiates in gen7, where we produce something like this: mov(8) vgrf10:UD, <low 32-bit> mov(8) vgrf10+0.4:UD, <high 32-bit> and then we use the result with a stride of 0, as in: mov(8) vgrf13:DF, vgrf10<0>:DF Although we could try to avoid this issue by producing different code for this by using writes with a stride of 2, that runs into other problems affecting gen7 and the fact is that any instruction that writes to a subreg_offset > 0 is a partial write so we should really recognize them as such. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/lower_simd_width: Fix registers written for split instructionsIago Toral Quiroga2016-05-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When the original instruction had a stride > 1, the combined registers written by the split instructions won't amount to the same register space written by the original instruction because the split instructions will use a stride of 1. The current code assumed otherwise and computed the number of registers written by split instructions as an equal share based on the relation between the lowered width and the original execution size of the instruction. It is only after the split, when we interleave the components of the result from the lowered instructions back into the original dst register, that the original stride takes effect and we write all the registers specified by the original instruction. Just make the number of register written the same as the vgrf space we allocate for the dst of the split instruction. Fixes crashes in fp64 tests produced as a result of assigning incorrectly the number of registers written by split instructions, which led to incorrect validation of the size of the writes against the allocated vgrf space. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: rename our lower_d2f pass to lower_d2xIago Toral Quiroga2016-05-104-4/+4
| | | | | | | Since it no longer handles conversions from double to float but from double to various other 32-bit types. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement i2d and u2dIago Toral Quiroga2016-05-101-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2i and d2uIago Toral Quiroga2016-05-102-1/+5
| | | | | | | These need the same treatment as d2f, so generalize our d2f lowering to cover these too. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement d2bIago Toral Quiroga2016-05-101-0/+13
| | | | | | v2: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: implement fsign() for doublesIago Toral Quiroga2016-05-101-17/+76
| | | | | | | | | | v2 (Sam): - Fix indentation (Kenneth) - Simplify code (Kenneth) v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add null_reg_dfIago Toral Quiroga2016-05-101-0/+7
| | | | | | | | Probably not needed since we fix the dst type of comparisons automatically, but for consistency with the rest of null_reg_* functions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: We only support 32-bit integer ALU operations for nowIago Toral Quiroga2016-05-101-3/+29
| | | | | | | Add asserts so we remember to address this when we enable 64-bit integer support, as suggested by Connor and Jason. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: handle fp64 opcodes in brw_do_channel_expressionsIago Toral Quiroga2016-05-101-9/+14
| | | | | | | | | | | | | | In the case of the pack opcode we are already doing the lowering in NIR, so no need to do it here. The unpack opcode operates on scalars, so it should not be lowered. In the case of frexp_sig and frexp_exp, they are lowered in lower_instructions, so we don't have to care about them. All the remaining opcodes involve conversions from and to doubles and are business as usual. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add support for f2d and d2fConnor Abbott2016-05-101-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add a pass for legalizing d2fConnor Abbott2016-05-104-0/+81
| | | | | | | | | We need to do this late, in order to avoid partial writes during the optimization loop. v2: Use subscript() instead of stride(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix dst width calculation in CSEConnor Abbott2016-05-101-1/+2
| | | | | | | | v2 (Sam): - Fix line width (Topi). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix regs_written in LOAD_PAYLOAD for doublesConnor Abbott2016-05-101-2/+6
| | | | | | | | v2: Account for the stride of the dst (Iago) Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix is_copy_payload() for doublesConnor Abbott2016-05-101-1/+1
| | | | | | | | | v2 (Sam): - LOAD_PAYLOAD treats each header source as a 32B block regardless of the datatype. Drop the change (Curro) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: fix compares for doublesConnor Abbott2016-05-101-3/+31
| | | | | | | | | | | | The destination has to have the same source as the type, or else the simulator will complain. As a result, we need to emit a CMP that outputs a 64-bit wide result and then do a strided MOV to pick out the low 32 bits of each channel. v2: Use subscript() instead of stride() (Curro) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: extend exec_size halving in the generatorConnor Abbott2016-05-101-6/+10
| | | | | | | | | | | | | The HW has a restriction that only vertical stride may cross register boundaries. Previously, this only mattered for SIMD16 instructions where we needed to use the same regioning parameters as the equivalent SIMD8 instruction but double the exec size. But we need to do the same splitting for 64-bit instructions as well as instructions with a stride of 2 (which effectively consume 64 bits per element). Fix up the code to do the right thing instead of special-casing SIMD16. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix assign_constant_locations() for doublesConnor Abbott2016-05-101-2/+6
| | | | | | | | | | | | | Uniform doubles will read two registers, in which case we need to mark both as being live. v2 (Sam): - Use a formula to get the number of registers read with proper units (Curro). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: use byte_offset() in offset() for uniformsConnor Abbott2016-05-101-3/+1
| | | | | | | | This makes things more consistent, and also fixes the offset calculation for double uniforms. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: handle uniforms in byte_offset()Connor Abbott2016-05-101-1/+5
| | | | | | | | v2: Do it only for uniforms (Iago) Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix type_size() for doublesConnor Abbott2016-05-101-1/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: optimize unpack doubleIago Toral Quiroga2016-05-101-4/+26
| | | | | | | | | | | | When we are actually unpacking from a double that we have previously packed from its 32-bit components we can bypass the pack operation and source from its arguments directly. v2 (Sam): - Fix line overflow (Topi) - Bail if the parent instruction's source is not SSA (Connor) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: optimize pack doubleIago Toral Quiroga2016-05-101-0/+29
| | | | | | | | | | | | | | When we are actually creating a double using values obtained from a previous unpack operation we can bypass the unpack and source from the original double value directly. v2: - Style changes (Topi) - Bail is parent instruction's src is not SSA (Connor) v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/nir: translate double pack/unpackConnor Abbott2016-05-101-0/+12
| | | | | | | | | v2 (Sam): - Fix line overflow (Topi). v3: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add a pass for lowering PACK opcodesConnor Abbott2016-05-104-0/+62
| | | | | | v2: Use subscript() instead of stride() (Curro) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add PACK opcodeConnor Abbott2016-05-105-1/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Introduce helper to extract a field from each channel of a register.Francisco Jerez2016-05-101-0/+28
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
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