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* i965: Don't flag gather quirks for Gen8+Chris Forbes2013-12-071-1/+1
| | | | | | | | | | | My understanding is that Broadwell retains the same SCS mechanism that Haswell has, so even if the underlying issue with this format is not fixed, the w/a will be applied in SCS rather than needing shader code. Signed-off-by: Chris Forbes <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: Allow CMS layout for multisample texturesChris Forbes2013-12-071-17/+1
| | | | | | | | | Now that all the pieces are in place, this should provide a nice performance boost for apps using multisample textures. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Sample from MCS surface when requiredChris Forbes2013-12-072-7/+40
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Sample from MCS surface when requiredChris Forbes2013-12-073-10/+41
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add shader opcode for sampling MCS surfaceChris Forbes2013-12-076-0/+16
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: Include bitfield in the sampler key for CMS layoutChris Forbes2013-12-072-0/+18
| | | | | | | | | | | | | | | | | | | | We need to emit extra shader code in this case to sample the MCS surface first; we can't just blindly do this all the time since IVB will sometimes try to access the MCS surface even if disabled. V3: Use actual MSAA layout from the texture's mt, rather then computing what would have been used based on the format. This is simpler and less fragile - there's at least one case where we might want to have a texture's MSAA layout change based on what the app does (CMS SINT falling back to UMS if the app ever attempts to render to it with a channel disabled.) This also obsoletes V2's 1/10 -- compute_msaa_layout can now remain an implementation detail of the miptree code. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/Gen7: Move decision to allocate MCS surface into intel_mipmap_createChris Forbes2013-12-071-6/+8
| | | | | | | | | | This gives us correct behavior for both renderbuffers (which previously worked) and multisample textures (which would never get an MCS surface allocated, even if CMS layout was selected) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: emit mcs info for multisample texturesChris Forbes2013-12-071-0/+5
| | | | | | | | Previously this was only done for render targets. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/wm: Set copy of sample mask in 3DSTATE_PS correctly for HaswellChris Forbes2013-12-071-2/+7
| | | | | | | | | | | | | | | The bspec says: "SW must program the sample mask value in this field so that it matches with 3DSTATE_SAMPLE_MASK" I haven't observed this to actually fix anything, but stumbled across it while adding the rest of the support for CMS layout for multisample textures. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: refactor sample mask calculationChris Forbes2013-12-074-33/+41
| | | | | | | | | Haswell needs a copy of the sample mask in 3DSTATE_PS; this makes that convenient. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Don't emit empty declaration warning for a struct specifierIan Romanick2013-12-061-1/+1
| | | | | | | | | | | | | | | | | The intention is that things like int; will generate a warning. However, we were also accidentally emitting the same warning for things like struct Foo { int x; }; Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68838 Reviewed-by: Kenneth Graunke <[email protected]> Cc: Aras Pranckevicius <[email protected]> Cc: "9.2 10.0" <[email protected]>
* st/xa: Bump major version number to 2Thomas Hellstrom2013-12-061-1/+1
| | | | | | | For some reason this was left out when the version was changed... Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* nvc0: fixup gk110 and up not being listed in various switch statementsBen Skeggs2013-12-067-13/+27
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* i965: Replace non-standard INLINE macro with "inline".Kenneth Graunke2013-12-056-22/+22
| | | | | | These are identical: main/compiler.h defines INLINE to "inline". Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Don't use GL types in files shared with intel-gpu-tools.Kenneth Graunke2013-12-056-1035/+1035
| | | | | | | | | sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-0572-621/+621
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Drop trailing whitespace from files shared with intel-gpu-tools.Kenneth Graunke2013-12-055-276/+276
| | | | | | Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <[email protected]>
* tools/trace: More tweaks to state dumping.José Fonseca2013-12-051-3/+12
| | | | | | - Ignore buffer format (it is totally arbitrary) - Initialize state. - Handle begin/end_query statements.
* trace: Reorder dumping of pipe_rasterizer_state.José Fonseca2013-12-051-3/+11
| | | | | | | Such that it matches the pipe_rasterizer_state declaration, making it easier to double-check that all state is being actually dumped. Trivial.
* trace: Dump pipe_sampler_state::seamless_cube_map.José Fonseca2013-12-051-0/+1
| | | | Trivial.
* radeonsi: Remove some stale XXX / FIXME commentsMichel Dänzer2013-12-052-5/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965: Emit better code for ir_unop_sign.Matt Turner2013-12-042-15/+49
| | | | | | | | | total instructions in shared programs: 1550449 -> 1550048 (-0.03%) instructions in affected programs: 15207 -> 14806 (-2.64%) Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: New peephole optimization to flatten IF/BREAK/ENDIF.Matt Turner2013-12-044-0/+99
| | | | | | | total instructions in shared programs: 1550713 -> 1550449 (-0.02%) instructions in affected programs: 7931 -> 7667 (-3.33%) Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Emit a MOV instead of a SEL if the sources are the same.Matt Turner2013-12-041-19/+23
| | | | | | | | One program affected. instructions in affected programs: 436 -> 428 (-1.83%) Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Extend SEL peephole to handle only matching MOVs.Matt Turner2013-12-041-3/+2
| | | | | | | | | | | | | | | | | | | | | | Before this patch, the following code would not be optimized even though the first two instructions were common to the then and else blocks: (+f0) IF MOV dst0 ... MOV dst1 ... MOV dst2 ... ELSE MOV dst0 ... MOV dst1 ... MOV dst3 ... ENDIF This commit extends the peephole to handle this case. No shader-db changes. Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: New peephole optimization to generate SEL.Matt Turner2013-12-044-0/+225
| | | | | | | | | | | | | | | | | | | | | fs_visitor::try_replace_with_sel optimizes only if statements whose "then" and "else" bodies contain a single MOV instruction. It also could not handle constant arguments, since they cause an extra MOV immediate to be generated (since we haven't run constant propagation, there are more than the single MOV). This peephole fixes both of these and operates as a normal optimization pass. fs_visitor::try_replace_with_sel is still arguably necessary, since it runs before pull constant loads are lowered. total instructions in shared programs: 1559129 -> 1545833 (-0.85%) instructions in affected programs: 167120 -> 153824 (-7.96%) GAINED: 13 LOST: 6 Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Add SEL() convenience function.Matt Turner2013-12-042-0/+2
| | | | Reviewed-by: Paul Berry <[email protected]>
* glsl: Use fabs() on floating point values.Matt Turner2013-12-041-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Print conditional mod in dump_instruction().Matt Turner2013-12-042-2/+6
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Externalize conditional_modifier for use in dump_instruction().Matt Turner2013-12-042-1/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Print argument types in dump_instruction().Matt Turner2013-12-042-2/+10
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Externalize reg_encoding for use in dump_instruction().Matt Turner2013-12-042-1/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Don't print swizzles for immediate values.Matt Turner2013-12-041-4/+6
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Print negate and absolute value for src args.Matt Turner2013-12-041-0/+7
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Add support for printing HW_REGs in dump_instruction().Matt Turner2013-12-041-0/+60
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Print ARF registers properly in dump_instruction().Matt Turner2013-12-041-2/+46
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't print extra (null) arguments in dump_instruction().Matt Turner2013-12-042-4/+4
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: Remove silly OR(..., 0x0) from ldexp() lowering.Matt Turner2013-12-041-3/+1
| | | | | | I translated copysign(0.0f, x) a little too literally. Reviewed-by: Eric Anholt <[email protected]>
* i965: Allow commuting the operands of ADDC for const propagation.Matt Turner2013-12-042-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Rename register_coalesce_2() -> register_coalesce().Matt Turner2013-12-042-6/+6
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Remove now useless register_coalesce() pass.Matt Turner2013-12-042-148/+0
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Let register_coalesce_2() eliminate self-moves.Matt Turner2013-12-041-1/+2
| | | | | | | | | This is the last thing that register_coalesce() still handled. total instructions in shared programs: 1561060 -> 1560908 (-0.01%) instructions in affected programs: 15758 -> 15606 (-0.96%) Reviewed-by: Eric Anholt <[email protected]>
* i965: Allow constant propagation into ASR and BFI1.Matt Turner2013-12-042-0/+4
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Document cur_* variables.Matt Turner2013-12-041-2/+5
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Remove ip & cur from brw_cfg.Matt Turner2013-12-042-26/+17
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Clean up cfg_t constructors.Matt Turner2013-12-049-23/+9
| | | | | | | parent_mem_ctx was unused since db47074a, so remove the two wrappers around create() and make create() the constructor. Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Throw out confusing make_list method.Matt Turner2013-12-042-15/+7
| | | | | | | make_list is just a one-line wrapper and was confusingly called by NULL objects. E.g., cur_if == NULL; cur_if->make_list(mem_ctx). Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Include only needed headers.Matt Turner2013-12-042-2/+3
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Remove unnecessary endif_stack.Matt Turner2013-12-041-3/+1
| | | | | | Unnecessary since last commit. Reviewed-by: Eric Anholt <[email protected]>
* i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.Matt Turner2013-12-042-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we made the basic block following an ENDIF instruction a successor of the basic blocks ending with IF and ELSE. The PRM says that IF and ELSE instructions jump *to* the ENDIF, rather than over it. This should be immaterial to dataflow analysis, except for if, break, endif sequences: START B1 <-B0 <-B9 0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F 0x00000110: (+f0) if(8) 0 0 null 0x00000000UD END B1 ->B2 ->B4 START B2 <-B1 break 0x00000120: break(8) 0 0 null 0D END B2 ->B10 START B3 0x00000130: endif(8) 2 null 0x00000002UD END B3 ->B4 The ENDIF block would have no parents, so dataflow analysis would generate incorrect results, preventing copy propagation from eliminating some instructions. This patch changes the CFG to make ENDIF start rather than end basic blocks, so that it can be the jump target of the IF and ELSE instructions. It helps three programs (including two fs8/fs16 pairs). total instructions in shared programs: 1561126 -> 1561060 (-0.00%) instructions in affected programs: 837 -> 771 (-7.89%) More importantly, it allows copy propagation to handle more cases. Disabling the register_coalesce() pass before this patch hurts 58 programs, while afterward it only hurts 11 programs. Reviewed-by: Eric Anholt <[email protected]>
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