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* anv: Advertise VK_KHR_external_semaphoreJason Ekstrand2017-08-151-3/+3
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Use DRM sync objects for external semaphores when availableJason Ekstrand2017-08-154-23/+128
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/gem: Add a drm syncobj supportJason Ekstrand2017-08-153-0/+80
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/drm: Pull in the i915 fence array APIJason Ekstrand2017-08-151-2/+28
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Implement support for exporting semaphores as FENCE_FDJason Ekstrand2017-08-155-9/+172
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/gem: Use EXECBUFFER2_WR when the FENCE_OUT flag is setJason Ekstrand2017-08-151-1/+4
| | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Submit a dummy batch when only semaphores are provided.Jason Ekstrand2017-08-154-3/+73
| | | | | | | | Vulkan allows you to do a submit whose only job is to wait on and trigger semaphores. The easiest way for us to support that right now is to insert a dummy execbuf. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Add a basic implementation of VK_KHX_external_semaphoreJason Ekstrand2017-08-154-9/+187
| | | | | | | | This patch adds an implementation based on DRM BOs. We don't actually advertise the extension yet because we want to add a couple more paths first. Reviewed-by: Lionel Landwerlin <[email protected]>
* clover/event: Include additional event statuses for clSetEventCallbackAaron Watry2017-08-151-1/+2
| | | | | | | | | | | | | | From CL 2.0 Section 5.11 (Event Objects): clSetEventCallback returns CL_SUCCESS if the function is executed successfully. Otherwise, it returns one of the following errors: ... CL_INVALID_VALUE if pfn_event_notify is NULL or if command_exec_callback_type is not CL_SUBMITTED , CL_RUNNING or CL_COMPLETE . Fixes: OpenCL CTS test_conformance/events/test_events callbacks Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* broadcom/vc4: Port NEON-code to ARM64Jonas Pfeil2017-08-151-0/+84
| | | | | | | | | | Changed all register and instruction names, works the same. v2: Rebase on build system changes (by anholt) v3: Fix build on clang (by anholt, reported by Rob) Signed-off-by: Jonas Pfeil <[email protected]> Tested-by: Rob Herring <[email protected]>
* broadcom/vc4: Build the vc4_tiling_lt_neon.c with -mfpu=neon on ARM.Eric Anholt2017-08-154-7/+24
| | | | | | | | | | | | | If you don't pass this, the compiler refuses to compile the assembly for pre-v7 CPUs. This also keeps us from building identical, non-NEON code on aarch64 and x86. Fixes: a373f77662c5 ("vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.") v2: Fix Android build by just appending NEON_C_SOURCES when ARCH_ARM_HAVE_NEON. Tested-by: Rob Herring <[email protected]>
* configure.ac: Introduce HAVE_ARM_ASM/HAVE_AARCH64_ASM and the -D flags.Eric Anholt2017-08-152-0/+28
| | | | | | | | | | | | | I've been trying to get away without these conditionals in vc4's NEON code, but it meant compiling extra unused code on x86, and build failing on ARMv6. v2: Use the _arm/_arm64 flags to simplify detection (suggested by Rob), but hide the _arm version under ARCH_ARM_HAVE_NEON to keep from trying to build this stuff for armv5te. Tested-by: Rob Herring <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* util: Fix build on old glibc.Eric Anholt2017-08-151-1/+3
| | | | | | | We need to link librt for u_thread.h's clock_gettime() call. Fixes: b822d9dd67b5 ("gallium/util: move u_queue.{c,h} to src/util") Reviewed-by: Matt Turner <[email protected]>
* broadcom: Add v3d_xml.h to gitignore.Eric Anholt2017-08-151-0/+1
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* broadcom: Add missing libexpat cflags for the decoder.Eric Anholt2017-08-151-0/+3
| | | | | The Raspbian ARMv6 cross compiler wasn't picking up my (amd64) system copy of the header the way that the system gcc and armhf cross-compile did.
* radv/gfx9: for fast clear use is_linear flag.Dave Airlie2017-08-161-1/+1
| | | | | | | | The legacy test won't work on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix tile swizzle handling for gfx9David Airlie2017-08-162-11/+8
| | | | | | | | This sets the tile swizzle up properly for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: handle GFX9 opaque metadataDavid Airlie2017-08-161-4/+5
| | | | | | | | port the opaque metadata changes from radeonsi for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: emit db_htile_surface reg on gfx9 as wellDavid Airlie2017-08-161-1/+2
| | | | | | | | This is also a GFX9 register. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: remove some leftover gfx6 descriptor setup.Dave Airlie2017-08-161-4/+0
| | | | | | | | | We set this later in the non-gfx9 path, just remove these bits from here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix set predication packet.Dave Airlie2017-08-161-9/+12
| | | | | | | | The predication packet changed format on GFX9, update the driver. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips2017-08-151-2/+2
| | | | | | | | | | | | | | | | BLEND_STATE packing was modified to be variable-length in: 9670124e31 genxml: Make BLEND_STATE command support variable length array. The initial gen10.xml still had the old, fixed-length style definition for BLEND_STATE. So gen10_upload_blend_state would overwrite the packed BLEND_STATE_ENTRYs with its own fixed array of all-zero entries when packing BLEND_STATE. This caused BLEND_STATE upload to not work at all. Fixes: aa416f515a ("i965/genxml: Add gen10.xml") Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: count uniform against storage when its bindlessTimothy Arceri2017-08-151-5/+13
| | | | | | | | | Gallium drivers use this code path so we need to account for bindless after all. Fixes: 365d34540f33 ("mesa: correctly calculate the storage offset for i915") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: disable CE by defaultMarek Olšák2017-08-153-8/+21
| | | | | | | | | It makes performance worse by a very small (hard to measure) amount. We've done extensive profiling of this feature internally. Cc: 17.1 17.2 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: initialise imported surface to 0.Dave Airlie2017-08-151-1/+1
| | | | | | | | | | | | For memobj imports we weren't setting the surface to 0, which meant sometimes we'd end up with tile_swizzle garbage, which would corrupt rendering. This seems to fix the image corruption on the imported memory objects in vrdashboard for me. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: correctly calculate the storage offsetTimothy Arceri2017-08-154-2/+165
| | | | | | | | | | When generating the storage offset for struct members we need to skip opaque types as they no longer have backing storage. Fixes: fcbb93e86024 ("mesa: stop assigning unused storage for non-bindless opaque types") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101983 Reviewed-by: Dave Airlie <[email protected]>
* mesa: correctly calculate the storage offset for i915Timothy Arceri2017-08-151-3/+1
| | | | | | | | | | | | When generating the storage offset for struct members we need to skip opaque types as they no longer have backing storage. Fixes: fcbb93e86024 ("mesa: stop assigning unused storage for non-bindless opaque types") V2: simplify since bindless will never be supported in this code Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101983 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Advertise the CCS modifierBen Widawsky2017-08-141-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | v2: Rename modifier to be more smart (Jason) FINISHME: Use the kernel's final choice for the fb modifier bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none Read bandwidth: 603.91 MiB/s Write bandwidth: 615.28 MiB/s bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ytile Read bandwidth: 571.13 MiB/s Write bandwidth: 555.51 MiB/s bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ccs Read bandwidth: 259.34 MiB/s Write bandwidth: 337.83 MiB/s v2: Move all references to the new fourcc code(s) to this patch. v3: Rebase, remove Yf_CCS (Daniel) Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Jason Ekstrand <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: More conservatively resolve external imagesJason Ekstrand2017-08-143-1/+47
| | | | | | | | | Instead of always doing a full resolve, only resolve the bits that are needed. This means that we only do a partial resolve when the miptree modifier is I915_FORMAT_MOD_Y_TILED_CCS. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Pretend that CCS modified images are two planesBen Widawsky2017-08-142-21/+40
| | | | | | | | | | | | | | | | v2: move is_aux into if block. (Jason) Use else block instead of goto (Jason) v3: Fix up logic for is_aux (Ben) Fix up size calculations and add FIXME (Ben) v4 (Jason Ekstrand): Use the aux_pitch in the image instead of calculating it Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/screen: Support import and export of surfaces with CCSJason Ekstrand2017-08-141-8/+71
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Allocate mcs_buf for an image's CCSBen Widawsky2017-08-141-4/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This code will disable actually creating these buffers for the scanout, but it puts the allocation in place. Primarily this patch is split out for review, it can be squashed in later if preferred. v2: assert(mt->offset == 0) in ccs creation (as requested by Topi) Remove bogus is_scanout check in miptree_release v3: Remove is_scanout assert in intel_miptree_create. It doesn't work with latest codebase - not sure it ever should have worked. v4: assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup (Topi) v5 (Jason Ekstrand): - Base the decision to allocate a CCS on the image modifier Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Support images with aux buffersBen Widawsky2017-08-141-0/+6
| | | | | | | | | | | | | | Previously images did not support any auxiliary compression surfaces (CCS, MCS, or HiZ). That's about to change. This patch just adds the fields to __DRIimageRec to make auxiliary surfaces possible. v2 (Jason Ekstrand): - Add an aux_pitch parameter as well as aux_offset Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCSJason Ekstrand2017-08-142-0/+8
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/screen: Stop redefining DRM_FORMAT_MOD_(INVALID|LINEAR)Jason Ekstrand2017-08-141-8/+0
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* drm-uapi/forcc: Pull in new modifiersJason Ekstrand2017-08-141-0/+31
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* i965/blorp: Correct type of src_format in call to ↵Scott D Phillips2017-08-141-1/+2
| | | | | | | | | | | | | | | | | | intel_miptree_texture_aux_usage intel_miptree_texture_aux_usage() takes an isl_format, but we are passing a mesa_format. clang warns: brw_blorp.c:305:52: warning: implicit conversion from enumeration type 'mesa_format' to different enumeration type 'enum isl_format' [-Wenum-conversion] intel_miptree_texture_aux_usage(brw, src_mt, src_format); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~ Fixes: fc1639e46d ("i965/blorp: Use texture/render_aux_usage for blits") Cc: "17.2" <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* st/va: change frame_idx from array to hash tableJulien Isorce2017-08-144-6/+31
| | | | | | | | | | | | | | | | | | | | | | | The picture_id was assumed to be a frame number so in 0-31. But the vaapi client gstreamer-vaapi uses the surfaces handles as identifier which are unsigned int. This bug can happen when using a lot of vaapi surfaces within the same process. Indeed Mesa/st/va increments a counter for the surface ID: mesa/util/u_handle_table.c::handle_table_add which starts from 0 and incremented by 1 at each call. So creating more than 32 surfaces was a problem. The following bug contains a test that reproduces the problem by running a couple of vaapih264enc in the same process. The above also explains why there was no pb when running them in separated processes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102006 Signed-off-by: Julien Isorce <[email protected]> Tested-by: Tomas Rataj <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-and-tested-by: Boyuan Zhang <[email protected]>
* configure: Trust LLVM >= 4.0 llvm-config --libs for shared librariesMichel Dänzer2017-08-141-28/+30
| | | | | | | | | | | No need to manually look for the library files anymore with current LLVM. This sidesteps the manual method failing when LLVM was built with -DLLVM_APPEND_VC_REV=ON. (This might already work with older versions of LLVM) Acked-by: Marek Olšák <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nv50/ir: clean up saturated values immediatelyIlia Mirkin2017-08-121-1/+6
| | | | | | | | | | | | Since we don't iterate to a fixed point, we can end up in situations where we have a SAT instruction + a long immediate. This is not legal. However since it's immediately computable, just run unary straight away to handle the situation. Fixes: 24a799ad35a82 ("nv50/ir: fix ConstantFolding with saturation") Reported-by: Tobias Klausmann <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: unlink values pre- and post-call to division functionIlia Mirkin2017-08-121-4/+3
| | | | | | | | | While technically correct, this can lead to e.g. getImmediate assuming that it can walk up the value chain. It could be fixed to not do this, but it seems easier and less error-prone to just not link the two values to save on one LValue object. Signed-off-by: Ilia Mirkin <[email protected]>
* i965: Guard GetBufferSubData's streaming memcpy load with USE_SSE41Kenneth Graunke2017-08-121-0/+2
| | | | | | | | | | This should hopefully fix build issues on 32-bit Android-x86. v2: s/USE_SSE4_1/USE_SS41/, caught by Gražvydas Ignotas. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102050 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Clean up intel_batchbuffer_init().Kenneth Graunke2017-08-123-12/+11
| | | | | | | | | | | | | Passing screen lets us get the kernel features, devinfo, and bufmgr, without needing container_of. This use of container_of could cause crashes due to issues with the "sample" macro parameter. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102062 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* gallium/radeon: only pass shader-specific debug flags to the disk shader cacheMarek Olšák2017-08-111-1/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/gfx9: fix the scissor bug workaroundMarek Olšák2017-08-111-3/+7
| | | | | | | | otherwise there is corruption in most apps. Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use the VI codepath for clamping ZMarek Olšák2017-08-112-12/+2
| | | | | | | | | This fixes corrupted shadows in Unigine Valley. The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8 for depth. Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* egl: Update headers from KhronosDaniel Stone2017-08-114-42/+673
| | | | | | Taken from egl-registry 7d68647c4dab. Signed-off-by: Daniel Stone <[email protected]>
* egl/dri2: Allow modifiers to add FDs to importsDaniel Stone2017-08-111-19/+19
| | | | | | | | | When using dmabuf import, make sure that the modifier is actually allowed to add planes to the base format, as implied by the comment. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* intel/compiler: properly size attribute wa_flags array for VulkanIago Toral Quiroga2017-08-111-1/+17
| | | | | | | | | | | | | | | | | | Mesa will map user defined vertex input attributes to slots starting at VERT_ATTRIB_GENERIC0 which gives us room for only 16 slots (up to GL_VERT_ATTRIB_MAX). This sufficient for GL, where we expose exactly 16 vertex attributes for user defined inputs, but in Vulkan we can expose up to 28 (which are also mapped from VERT_ATTRIB_GENERIC0 onwards) so we need to account for this when we scope the size of the array of attribute workaround flags that is used during the brw_vertex_workarounds NIR pass. This prevents out-of-bounds accesses in that array for NIR shaders that use more than 16 vertex input attributes. Fixes: dEQP-VK.pipeline.vertex_input.max_attributes.* Acked-by: Lionel Landwerlin <[email protected]>
* glsl: stop cloning builtin fuctions _mesa_glsl_find_builtin_function()Timothy Arceri2017-08-111-10/+1
| | | | | | | | | | | | | | | | | | | | | The cloning was introduced in f81ede469910d to fix a problem with shaders including IR that was owned by builtins. However the approach of cloning the whole function each time we reference a builtin lead to a significant reduction in the GLSL IR compilers performance. The previous patch fixes the ownership problem in a more precise way. So we can now remove this cloning. Testing on a Ryzen 7 1800X shows a ~15% decreases in compiling the Deus Ex: Mankind Divided shaders on radeonsi (which take 5min+ on some machines). Looking just at the GLSL IR compiler the speed up is ~40%. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
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