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* meta: Fix ClearTexture with GL_DEPTH_COMPONENT.Kenneth Graunke2017-12-061-9/+14
* meta: Initialize depth/clear values on declaration.Kenneth Graunke2017-12-061-5/+2
* glsl: get correct member type when processing xfb ifc arraysTimothy Arceri2017-12-071-2/+4
* r600/sb: do not convert if-blocks that contain indirect array accessGert Wollny2017-12-073-2/+5
* r600: add support for compute grid/block sizes. (v2)Dave Airlie2017-12-064-3/+100
* r600: handle image/buffer sizes correctly.Dave Airlie2017-12-063-4/+21
* r600/compute: add support for emitting compute image/buffer atomsDave Airlie2017-12-061-1/+9
* r600/compute: handle atomic counters in compute state.Dave Airlie2017-12-061-0/+9
* r600/compute: add support for TGSI compute shaders. (v1.1)Dave Airlie2017-12-062-28/+103
* r600/shader: add compute support to shader assemblerDave Airlie2017-12-061-0/+14
* r600/texture: drop lowering 1d/2d images to linear.Dave Airlie2017-12-061-8/+0
* mesa: define nir_spirv_supported_capabilitiesAlejandro Piñeiro2017-12-062-13/+15
* anv: fix a case statement in GetMemoryFdPropertiesKHRFredrik Höglund2017-12-061-1/+1
* radv: fix a case statement in GetMemoryFdPropertiesKHRFredrik Höglund2017-12-061-1/+1
* meson: fix keyword argument in declare_dependency()Eric Engestrom2017-12-062-2/+2
* i965: include brw_pipe_control.h in the tarballEmil Velikov2017-12-061-0/+1
* mesa: document _mesa_extension_override_* variablesEmil Velikov2017-12-061-0/+9
* docs: annotate MESA_program_debug as obsoleteEmil Velikov2017-12-061-1/+1
* swr/scons: Fix another intermittent build failureGeorge Kyriazis2017-12-061-0/+1
* radeonsi: make const and stream uploaders allocate read-only memoryMarek Olšák2017-12-061-2/+5
* radeonsi: use a separate allocator for fine fencesMarek Olšák2017-12-063-1/+9
* radeonsi/gfx9: make shader binaries use read-only memoryMarek Olšák2017-12-065-3/+13
* winsys/amdgpu: make IBs use read-only memoryMarek Olšák2017-12-061-0/+1
* radeonsi: print the buffer list for CHECK_VMMarek Olšák2017-12-061-0/+1
* radeonsi: allow DMABUF exports for local buffersMarek Olšák2017-12-061-1/+4
* radeonsi: always place sparse buffers in VRAMNicolai Hähnle2017-12-062-2/+6
* radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE checkNicolai Hähnle2017-12-061-1/+1
* i965/fs: Use untyped_surface_read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-7/+20
* i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit regJose Maria Casanova Crespo2017-12-061-15/+43
* anv: Enable SPV_KHR_16bit_storage and VK_KHR_16bit_storage for SSBO/UBOAlejandro Piñeiro2017-12-063-0/+15
* i965/fs: Enables 16-bit load_ubo with samplerJason Ekstrand2017-12-061-7/+14
* i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit componentsJose Maria Casanova Crespo2017-12-062-0/+71
* i965/fs: Use byte scattered read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-1/+13
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-069-1/+94
* i965/fs: Predicate byte scattered writes if neededAlejandro Piñeiro2017-12-061-1/+14
* i965/fs: Use byte_scattered_write on 16-bit store_ssboAlejandro Piñeiro2017-12-061-20/+45
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-069-0/+118
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-063-0/+39
* i965/fs: Enable rounding mode on f2f16 opsAlejandro Piñeiro2017-12-061-0/+18
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-065-0/+62
* i965: Add support for control registerJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Handle 32-bit to 16-bit conversionsAlejandro Piñeiro2017-12-061-0/+25
* i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_typeAlejandro Piñeiro2017-12-061-3/+0
* i965: Support for 16-bit base types in helper functionsJose Maria Casanova Crespo2017-12-063-0/+25
* i965/vec4: Handle 16-bit types at type_size_xvec4Alejandro Piñeiro2017-12-061-0/+3
* spirv/nir: Add support for SPV_KHR_16bit_storageEduardo Lima Mitev2017-12-062-0/+8
* spirv: Enable FPRoundingMode decorator to nir operationsJose Maria Casanova Crespo2017-12-061-0/+33
* spirv/nir: Handle 16-bit typesEduardo Lima Mitev2017-12-062-19/+114
* nir: Handle fp16 rounding modes at nir_type_conversion_opJose Maria Casanova Crespo2017-12-065-6/+28
* nir: Populate conversion opcodes to 16-bit typesEduardo Lima Mitev2017-12-061-1/+1
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