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* gallivm: don't calculate square root of rho if we use accurate rho methodRoland Scheidegger2013-08-301-39/+74
| | | | | | | | | | | | | | | | | | | | While a sqrt here and there shouldn't hurt much (depending on the cpu) it is possible to completely omit it since rho is only used for calculating lod and there log2(x) == 0.5*log2(x^2). Depending on the exact path taken for calculating lod this means we get a simple mul instead of sqrt (in case of nearest mip filter in fact we don't need to replace the sqrt with something else at all), only in some not very useful path this doesn't work (combined brilinear calculation of int level and fractional lod, accurate rho calc but brilinear filtering seems odd). Apart from being faster as an added bonus this should increase our crappy fractional accuracy of lod, since fast_log2 is only good for ~3bits and this should increase accuracy by one bit (though not used if dimension is just one as we'd need an extra mul there as we never had the squared rho in the first place). v2: use separate ilog2_sqrt function if we have squared rho. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: refactor num_lods handlingRoland Scheidegger2013-08-304-131/+169
| | | | | | | | | | | | | This is just preparation for per-pixel (or per-quad in case of multiple quads) min/mag filter since some assumptions about number of miplevels being equal to number of lods no longer holds true. This change does not change behavior yet (though theoretically when forcing per-element path it might be slower with different min/mag filter since the code will respect this setting even when there's no mip maps now in this case, so some lod calcs will be done per-element just ultimately still the same filter used for all pixels). Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: Early return if no depth or stencil on release builds.Vinson Lee2013-08-291-0/+1
| | | | | | | Fixes "Missing break in switch" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno: pipe loader for either kgsl or msmRob Clark2013-08-294-10/+39
| | | | | | | | The downstream android kernel driver is "kgsl", the upstream drm/kms driver is called "msm". Since libdrm_freedreno handles the differences between the two, we need to load the same thing for either device. Signed-off-by: Rob Clark <[email protected]>
* freedreno: updates for msm drm/kms driverRob Clark2013-08-298-30/+55
| | | | | | | There where some small API tweaks in libdrm_freedreno to enable support for msm drm/kms driver. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: handle sync flags betterRob Clark2013-08-291-16/+34
| | | | | | | | We need to set the flag on all the .xyzw components that are written by the instruction, not just on .x. Otherwise a later use of rN.y (for example) will not trigger the appropriate sync bit to be set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: better const handlingRob Clark2013-08-291-90/+121
| | | | | | | | | Seems like most/all instructions have some restrictions about const src registers. In seems like the 2 src (cat2) instructions can take at most one const, and the 3 src (cat3) instructions can take at most one const in the first 2 arguments. And so on. Handle this properly now. Signed-off-by: Rob Clark <[email protected]>
* glsl: Allow precision qualifiers for sampler typesAnuj Phogat2013-08-291-8/+21
| | | | | | | | | | | | | | | | | | | | | | | GLSL 1.30 doesn't allow precision qualifiers on sampler types, but in GLSL ES, sampler types are also allowed. This seems like an oversight (since the intention of including these in GLSL 1.30 is to allow compatibility with ES shaders). Currently, Mesa allows "default" precision qualifiers to be set for sampler types in GLSL (commit d5948f2). This patch makes it follow GLSL ES rules and also allow declaring sampler variables with a precision qualifier in GLSL 1.30 (and later). e.g. uniform lowp sampler2D sampler; This fixes a shader compilation error in Khronos OpenGL conformance test "depth_texture_mipmap". V2: Update comments. Signed-off-by: Ian Romanick <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: <[email protected]>
* glsl: Add heuristics to print floating-point numbers better.Matt Turner2013-08-2915-32/+42
| | | | | v2: Fix *.expected files to match. Reviewed-by: Paul Berry <[email protected]>
* radeonsi: Make sure libdrm_radeon headers are picked up from the right placeJonathan Gray2013-08-292-2/+3
| | | | | | And remove libdrm/ from a winsys include statement. Signed-off-by: Jonathan Gray <[email protected]>
* draw: fix point/line/triangle determination in draw_need_pipeline()Brian Paul2013-08-291-25/+6
| | | | | | The previous point/line/triangle() functions didn't handle GS primitives. Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/uvd: fix MPEG2/4 ref frame index limitChristian König2013-08-291-2/+2
| | | | | | Otherwise the first few frames have an incorrect reference index. Signed-off-by: Christian König <[email protected]>
* nouveau: Copy m4x4 and m8x8 separately.Vinson Lee2013-08-281-1/+2
| | | | | | Silences Coverity "Out-of-bounds access" defect. Signed-off-by: Vinson Lee <[email protected]>
* i965: Allocate just enough space for user clip planes in uniform arrays.Kenneth Graunke2013-08-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | Previously, we allocated space in brw_vs_prog_data's params and pull_params arrays for MAX_CLIP_PLANES vec4s---even when it wasn't necessary. On a 64-bit architecture, this used 0.5 kB of space (8 clip planes * 4 floats per plane * 8 bytes per float pointer * 2 arrays of pointers = 512 bytes). Since this cost was per-vertex shader, it added up. Conveniently, we already store the number of clip plane constants in the program key. By using that, we can allocate the exact amount of space needed. For the common case where user clipping is disabled, this means 0 bytes. While we're here, mention exactly what code requires this extra space, since it wasn't obvious. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Silence unused variable warning in release buildChad Versace2013-08-281-1/+1
| | | | | | | | | | | Use `(void) success;` to silence this warning: i965/brw_vs.c:481:12: warning: unused variable 'success' [-Wunused-variable] bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram, Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* docs: minor fixes for 9.2 release notesBrian Paul2013-08-271-2/+2
| | | | | Fix incorrect </li> tag, fix language. (cherry picked from commit 2377205bcb3bb0b5db48772224f5f80f2cf9abf7)
* docs: Add news item for 9.2 releaseIan Romanick2013-08-271-0/+7
| | | | Signed-off-by: Ian Romanick <[email protected]>
* docs: Import 9.2 release notesIan Romanick2013-08-271-4/+149
| | | | Signed-off-by: Ian Romanick <[email protected]>
* mesa/main: Check for 0 size draws after validation.Fabian Bieler2013-08-272-21/+42
| | | | | | | | | | | | | | | | | | | When validating draw parameters move check for 0 draw count last (drawing with count 0 is not an error), so that other parameters (e.g.: the primitive type) are validated and the correct errors (if applicable) are generated. >From the OpenGL 3.3 spec page 33 (page 48 of the PDF): "[Regarding DrawArraysOneInstance, in terms of which other draw operations are defined:] If count is negative, an INVALID_VALUE error is generated." This patch also changes the bahavior of MultiDrawElements to perform the draw operation if some primitive's index counts are zero. Signed-off-by: Fabian Bieler <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Add built-ins from ARB_shader_bit_encoding to ARB_gpu_shader5.Matt Turner2013-08-271-0/+20
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Add support for translating ir_triop_fma into MAD.Matt Turner2013-08-272-0/+12
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add support for translating ir_triop_fma into MAD.Matt Turner2013-08-274-0/+10
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Assert that ir_expressions are usable by 3-src instructions.Matt Turner2013-08-271-0/+1
| | | | | | | MAD will be generated directly from ir_triop_fma, so this assertion checks that all ir_expressions are usable. Reviewed-by: Paul Berry <[email protected]>
* glsl: Add support for new fma built-in in ARB_gpu_shader5.Matt Turner2013-08-276-0/+22
| | | | | | v2: Add constant folding support. Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add new fma built-in IR and prototype from ARB_gpu_shader5.Matt Turner2013-08-272-0/+34
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r300g: enable MSAA on r300-r400, be careful about using color compressionMarek Olšák2013-08-274-5/+14
| | | | | | | | | | MSAA was tested by one user on RS690 and it works for him with color compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM. Since we don't have hardware documentation about which chipsets actually have CMASK RAM, I had to take a guess based on the presence of HiZ. Reviewed-by: Alex Deucher <[email protected]>
* configure.ac: Bump Wayland requirement to 1.2.0Fabio Pedretti2013-08-271-1/+1
| | | | | | Since 8d29b52 wayland 1.2.0 is required. Reviewed-by: Chad Versace <[email protected]>
* draw: clean up setting stream out information a bitRoland Scheidegger2013-08-279-34/+39
| | | | | | | | | | | | | | | | | In particular noone is interested in the vertex count, so drop that, and also drop the duplicated num_primitives_generated / so.primitives_storage_needed variables in drivers. I am unable for now to figure out if primitives_storage_needed in SO stats (used for d3d10) should increase if SO is disabled, though the equivalent num_primitives_generated used for OpenGL definitely should increase. In any case we were only counting when SO is active both in softpipe and llvmpipe anyway so don't pretend there's an independent num_primitives_generated counter which would count always. (This means the PIPE_QUERY_PRIMITIVES_GENERATED count will still be wrong just as before, should eventually fix this by doing either separate counting for this query or adjust the code so it always counts this even if SO is inactive depending on what's correct for d3d10.) Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-273-18/+20
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* softpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-272-18/+17
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* glsl: Disallow uniform block layout qualifiers on non-uniform block vars.Matt Turner2013-08-261-4/+13
| | | | | | Cc: 9.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68460 Reviewed-by: Ian Romanick <[email protected]>
* Fixed and/or order mistake, resulting in compiling llvmpipe without llvm ↵Kristian Lehmann2013-08-261-2/+2
| | | | | | | | installed Cc: 9.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68544 Reviewed-by: Matt Turner <[email protected]>
* i915: Optimize SEQ and SNE when two operands are uniformsIan Romanick2013-08-261-12/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SEQ and SNE are not native i915 instructions, so they each generate at least 3 instructions. If both operands are uniforms or constants, we get 5 instructions like: U[1] = MOV CONST[1] U[0].xyz = SGE CONST[0].xxxx, U[1] U[1] = MOV CONST[1].-x-y-z-w R[0].xyz = SGE CONST[0].-x-x-x-x, U[1] R[0].xyz = MUL R[0], U[0] This code is stupid. Instead of having the individual calls to i915_emit_arith generate the moves to utemps, do it in the caller. This results in code like: U[1] = MOV CONST[1] U[0].xyz = SGE CONST[0].xxxx, U[1] R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w R[0].xyz = MUL R[0], U[0] This allows fs-temp-array-mat2-index-col-wr and fs-temp-array-mat2-index-row-wr to fit in hardware limits (instead of falling back to software rasterization). NOTE: Without pending patches to the piglit tests, these tests will now fail. This is an unrelated, pre-existing issue. v2: Copy most of the body of the commit message into comments in the code. Suggested by Eric. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copiesTom Stellard2013-08-261-1/+1
| | | | | | CC: "9.2" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/clover: Add event to deps even if it has been triggeredNiels Ole Salscheider2013-08-261-1/+1
| | | | | | | | The command is submitted once the event has been triggered, but it might not have completed yet. Therefore, we have to add it to deps in order to wait on it. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/clover: Profiling supportNiels Ole Salscheider2013-08-263-18/+142
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* tgsi_build: fix order of arguments for ind register buildDave Airlie2013-08-271-1/+1
| | | | | | | This was broken when arrayid was added. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: finish declaration parsing for arrays.Dave Airlie2013-08-271-1/+31
| | | | | | | | | I previously fixed this partly in 9e8400f4c95bde1f955c7977066583b507159a10, however I didn't go far enough in testing it, now when I parse a TGSI shader with arrays in it my iterator can see the ArrayID set to the proper value. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: replace 0 with PIPE_OK in a few placesBrian Paul2013-08-263-5/+5
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* swrast: init i0, i1 values to silence warningsBrian Paul2013-08-261-0/+1
| | | | Reviewed-by: Chad Versace <[email protected]>
* mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT()Brian Paul2013-08-261-1/+2
| | | | | | to silence gcc 4.8.1 warnings. And improve the ASSERT(0) call. Reviewed-by: Chad Versace <[email protected]>
* glsl: init limit=0 to silence uninitialized var warningBrian Paul2013-08-261-1/+1
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Allocate register set once at context creation.Kenneth Graunke2013-08-263-4/+6
| | | | | | | | | | Now that we use a fixed set of register classes, we can set up the register set and conflict graphs once, at context creation, rather than on every VS compile. This is obviously less expensive, and also what we already do in the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Move base_reg_count computation to brw_alloc_reg_set().Kenneth Graunke2013-08-261-3/+4
| | | | | | | | We're soon going to be calling brw_alloc_reg_set() from outside of the visitor, where we don't have the precomputed "max_grf" variable handy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Expose the payload registers to the register allocator.Kenneth Graunke2013-08-262-6/+36
| | | | | | | | | | | | | | | For now, nothing else can get allocated over them. That may change at some point in the future. This also means that base_reg_count can be computed without knowing the number of registers used for the payload, which is required if we want to allocate the register set once at context creation time. See commit 551e1cd44f6857f7e29ea4c8f892da5a97844377, which implemented virtually identical code in the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Use a fixed set of register classes.Kenneth Graunke2013-08-261-37/+13
| | | | | | | | | | | Arrays, structures, and matrices use large VGRFs of arbitrary sizes. However, split_virtual_grfs() breaks those down into VGRFs of size 1. For reference, commit 5d90b988791e51cfb6413109271ad102fd7a304c is the analogous change to the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Allow C++ type safety in the use of enum brw_urb_write_flags.Paul Berry2013-08-267-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (From a suggestion by Francisco Jerez) If an enum represents a bitfield of flags, e.g.: enum E { A = 1, B = 2, C = 4, D = 8, }; then C++ normally prohibits statements like this: enum E x = A | B; because A and B are implicitly converted to ints before OR-ing them, and an int can't be stored in an enum without a type cast. C, on the other hand, allows an int to be implicitly converted to an enum without casting. In the past we've dealt with this situation by storing flag bitfields as ints. This avoids ugly casting at the expense of some type safety that C++ would normally have offered (e.g. we get no warning if we accidentally use the wrong enum type). However, we can get the best of both worlds if we override the | operator. The ugly casting is confined to the operator overload, and we still get the benefit of C++ making sure we don't use the wrong enum type. v2: Remove unnecessary comment and unnecessary use of "enum" keyword. Use static_cast. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Remove redundant (and uninitialized) field vec4_generator::ctx.Paul Berry2013-08-262-3/+2
| | | | | | | | | | | | | We never noticed that this field was uninitialized because it is only used in an error path that reports internal Mesa errors. But it's silly to have it around anyway because &brw->ctx is equivalent. Should fix Coverity defect CID 1063351: Uninitialized pointer field (UNINIT_CTOR) /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp: 148 Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't try to fall back when creating unrecognized program targets.Paul Berry2013-08-261-1/+2
| | | | | | | | | | | | | | If brwNewProgram is asked to create a program for an unrecognized target, don't bother falling back on _mesa_new_program(). That just hides bugs. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> v2: Use assert() rather than _mesa_problem(). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* radeonsi: Also set the depth component mask bit for stencil-only exportsMichel Dänzer2013-08-261-1/+4
| | | | | | | | The stencil values come out wrong without this for some reason. 50 more little piglits. Cc: [email protected]
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