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* Revert "radeonsi: avoid syncing the driver thread in si_fence_finish"Timothy Arceri2018-09-183-52/+40
* v3d: Switch from FLUSH_ALL_STATE to FLUSH for ending our bin CLs.Eric Anholt2018-09-171-6/+6
* v3d: Stop clearing the OQ state at the end of the job.Eric Anholt2018-09-173-18/+1
* v3d: Always emit a TF disable at the start of drawing on V3D 4.x.Eric Anholt2018-09-173-10/+8
* build: Don't overlink gallium xlib targetDylan Baker2018-09-172-2/+1
* move pthread_setaffinity_np check to the build systemDylan Baker2018-09-173-4/+23
* mesa: FramebufferParameteri parameter checkingFritz Koenig2018-09-171-0/+1
* mesa: Additional FlipY applicationsFritz Koenig2018-09-172-3/+3
* radv: Use build ID if available for cache UUID.Bas Nieuwenhuizen2018-09-171-8/+35
* radv: enable shaderInt16 capabilitySamuel Pitoiset2018-09-172-1/+2
* ac: add 16-bit support to ac_build_bitfield_reverse()Samuel Pitoiset2018-09-171-0/+5
* ac: add 16-bit support to ac_build_bit_count()Samuel Pitoiset2018-09-171-0/+5
* ac: add 16-bit support to ac_find_lsb()Samuel Pitoiset2018-09-171-2/+13
* ac: add 16-bit support to ac_build_umsb()Samuel Pitoiset2018-09-171-2/+16
* ac: add 16-bit support to ac_build_isign()Samuel Pitoiset2018-09-171-5/+16
* ac: add 16-bit constant values for zero and oneSamuel Pitoiset2018-09-172-0/+4
* ac: add ac_build_bifield_reverse() helperSamuel Pitoiset2018-09-173-1/+26
* ac: add ac_build_bit_count() helperSamuel Pitoiset2018-09-173-6/+31
* radv: fix use of unreachable() in the meta blit pathSamuel Pitoiset2018-09-171-4/+4
* Revert "radv: Optimize rebinding the same descriptor set."Samuel Pitoiset2018-09-171-7/+1
* radv: fix descriptor pool allocation sizeSamuel Pitoiset2018-09-171-1/+2
* anv/query: Add an emit_srm helperJason Ekstrand2018-09-171-32/+21
* anv: Add a mi_memset and use it for zeroing queriesJason Ekstrand2018-09-173-12/+23
* anv/query: Use anv_address everywhereJason Ekstrand2018-09-171-57/+64
* anv/query: Write both dwords in emit_zero_queriesJason Ekstrand2018-09-171-0/+5
* anv/query: Increment an index while writing resultsJason Ekstrand2018-09-171-36/+31
* i965/fs: Don't propagate conditional modifiers from integer compares to addsIan Romanick2018-09-171-1/+9
* radv: Only allow 16 user SGPRs for compute on GFX9+.Bas Nieuwenhuizen2018-09-161-1/+1
* radv: Set the user SGPR MSB for Vega.Bas Nieuwenhuizen2018-09-161-0/+1
* radv: Optimize rebinding the same descriptor set.Bas Nieuwenhuizen2018-09-161-1/+7
* r600/sb: use safe math optimizations when TGSI contains precise operationsGert Wollny2018-09-153-1/+5
* android: broadcom/cle: export the broadcom top level path headersMauro Rossi2018-09-151-0/+2
* android: broadcom/cle: add gallium include pathMauro Rossi2018-09-151-0/+2
* android: broadcom/genxml: fix collision with intel/genxml header-gen macroMauro Rossi2018-09-151-5/+5
* anv/memcpy: fix build after starting to use addressesCaio Marcelo de Oliveira Filho2018-09-141-2/+2
* anv/cmd_buffer: Take an address in emit_lrmJason Ekstrand2018-09-141-17/+16
* anv/memcpy: Use addresses instead of bo+offsetJason Ekstrand2018-09-143-35/+34
* anv/so_memcpy: Use the correct SO_BUFFER size on gen8+Jason Ekstrand2018-09-141-1/+1
* ac: fix get_image_coords() for radeonsiTimothy Arceri2018-09-151-1/+2
* gallium/util: don't let child processes inherit our thread affinityMarek Olšák2018-09-141-4/+32
* gallium/util: start with a random L3 cache index for AMD ZenMarek Olšák2018-09-141-4/+16
* st/mesa: Validate the result of pipe_transfer_map in make_texture (v2)Josh Pieper2018-09-141-8/+12
* radv: emit the initial config only once in the preamblesSamuel Pitoiset2018-09-144-50/+48
* radv: fix setting global locations for indirect descriptorsSamuel Pitoiset2018-09-141-1/+0
* radv: fix flushing indirect descriptorsSamuel Pitoiset2018-09-141-3/+9
* radv: fix GPU hangs with 32-bit indirect descriptorsSamuel Pitoiset2018-09-141-3/+5
* radv: handle loc->indirect correctly for the first descriptorSamuel Pitoiset2018-09-142-11/+10
* radv: bump the maximum number of arguments to 64Samuel Pitoiset2018-09-141-1/+1
* radv: tidy up ac_setup_rings() for the GSVS ringsSamuel Pitoiset2018-09-141-13/+34
* radv: fix setting the number of entries for GSVS on VI+Samuel Pitoiset2018-09-141-3/+0
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