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* egl: move eglQuerySurface() fallback to eglapi.cEric Engestrom2019-06-252-2/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* egl: move eglQueryContext() fallback to eglapi.cEric Engestrom2019-06-252-3/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* egl: move eglGetConfigAttrib() fallback to eglapi.cEric Engestrom2019-06-252-3/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* egl: move eglChooseConfig() fallback to eglapi.cEric Engestrom2019-06-252-3/+6
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* egl: move eglGetConfigs() fallback to eglapi.cEric Engestrom2019-06-252-2/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* freedreno/a5xx: fix batch leak in fd5 blitter pathRob Clark2019-06-241-0/+1
| | | | | Fixes: 3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: don't set spi_ps_input_* for monolithic shadersMarek Olšák2019-06-241-13/+26
| | | | | | | | The driver doesn't use these values and ac_rtld has assertions expecting the value of 0. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: rename and re-document cache flush flagsMarek Olšák2019-06-2410-64/+66
| | | | | | | SMEM and VMEM caches are L0 on gfx10. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix AMD_DEBUG=nofmaskMarek Olšák2019-06-244-14/+20
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: flatten the switch for DPBB tunablesMarek Olšák2019-06-241-14/+4
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: set the calling convention for inlined function callsMarek Olšák2019-06-244-2/+13
| | | | | | | otherwise the behavior is undefined Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: refactor si_update_vgt_shader_configNicolai Hähnle2019-06-242-28/+60
| | | | | | | | | | We'll have to extend this at some point, and using a bitfield union in this way makes it easier to get the right index without excessive branching. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/rtld: update the ELF representation of LDS symbolsNicolai Hähnle2019-06-241-7/+27
| | | | | | | | | | | | | | | | The initial prototype used a processor-specific symbol type, but feedback suggests that an approach using processor-specific section name that encodes the alignment analogous to SHN_COMMON symbols is preferred. This patch keeps both variants around for now to reduce problems with LLVM compatibility as we switch branches around. This also cleans up the error reporting in this function. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: remove addrlib_family_rev_idMarek Olšák2019-06-243-108/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* docs: update calendar, add news item and link release notes for 19.0.7Dylan Baker2019-06-243-7/+12
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* docs: Add SHA256 sums for 19.0.7Dylan Baker2019-06-241-1/+2
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* Docs add 19.0.7 release notesDylan Baker2019-06-241-0/+149
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* glsl: Don't increase the iteration count when there are no terminatorsIan Romanick2019-06-241-1/+7
| | | | | | | | | | | | | | | | | | | Incrementing the iteration count was intended to fix an off-by-one error when the first terminator was superseded by a later terminator. If there is no first terminator or later terminator, there is no off-by-one error. Incrementing the loop count creates one. This can be seen in loops like: do { if (something) { // No breaks or continues here. } } while (false); Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Abel Briggs <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110953 Fixes: 646621c66da ("glsl: make loop unrolling more like the nir unrolling path")
* freedreno: Only upload the used part of UBO0 to the constant buffer.Eric Anholt2019-06-242-5/+13
| | | | | | | | | | We were pessimistically uploading all of it in case of indirection, but we can just bump that when we encounter indirection. total constlen in shared programs: 2529623 -> 2485933 (-1.73%) Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: Stop treating UBO 0 specially in UBO uploading.Eric Anholt2019-06-243-40/+1
| | | | | | | | | ir3_nir_analyze_ubo_ranges() has already told us how much of cb0 we need to upload (all of it, since it will lower indirect UBO 0 accesses from load_ubo back to indirection on the constant buffer). Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: Clamp UBO uploads to the constlen decided by the shader.Rob Clark2019-06-241-0/+11
| | | | | | | | | | | | If the NIR-level analysis decided to move UBO loads to the constant file, but the backend decided not to load those constants, we could upload past the end of constlen. This is particularly relevant for pre-a6xx, where we emit a different constlen between bin and render variants. (Fix by Rob, commit message by anholt) Reviewed-by: Eric Anholt <[email protected]>
* panfrost: Allow up to 16 UBOsAlyssa Rosenzweig2019-06-241-1/+1
| | | | | | This is the hardware max, as far as I can tell. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: DRY between shader stage setupAlyssa Rosenzweig2019-06-241-19/+36
| | | | | | | Just a little spring cleanup, extending UBOs to vertex shaders in the process. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement UBO readsAlyssa Rosenzweig2019-06-241-14/+51
| | | | | | | UBOs and uniforms now use a common code path with an explicit `index` argument passed, enabling UBO reads. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Handle disabled/empty UBOsAlyssa Rosenzweig2019-06-241-1/+13
| | | | | | | Prevents an assert(0) later in this (not so edge) case. We still have to have a dummy there. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Identify "uniform buffer count" bitsAlyssa Rosenzweig2019-06-243-22/+21
| | | | | | | We've known about this for a while, but it was never formally in the machine header files / decoder, so let's add them in. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Upload UBOsAlyssa Rosenzweig2019-06-241-0/+31
| | | | | | | Now that all the counting is sorted, it's a matter of passing along a GPU address and going. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allow for dynamic UBO countAlyssa Rosenzweig2019-06-241-11/+16
| | | | | | | We already uploaded UBOs, but only a fixed number (1) for uniforms; let's upload as many as we compute we need. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Report UBO countAlyssa Rosenzweig2019-06-241-2/+15
| | | | | | | | We look at the highest set bit in the UBO enable mask to work out the maximum indexable UBO, i.e. the UBO count as we need to report to the hardware. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Constant buffer refactorAlyssa Rosenzweig2019-06-242-38/+34
| | | | | | | We refactor panfrost_constant_buffer to mirror v3d's constant buffer handling, to enable UBOs as well as a single set of uniforms. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Replace varyings for point spritesAlyssa Rosenzweig2019-06-241-1/+27
| | | | | | | This doesn't handle Y-flipping, but it's good enough to render the stars in Neverball. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Track point sprites in fragment shader keyAlyssa Rosenzweig2019-06-242-3/+39
| | | | | | | In preparation for lowering point sprites, track them like we track alpha testing state. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* i965: Move resources lowering after NIR linkingCaio Marcelo de Oliveira Filho2019-06-243-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Those either depend on information filled by the NIR linking steps OR are restricted by those: - gl_nir_lower_samplers: depends on UniformStorage being set by the linker. - brw_nir_lower_image_load_store: After 6981069fc80 "i965: Ignore uniform storage for samplers or images, use binding info" we want this pass to happen after gl_nir_lower_samplers. - gl_nir_lower_buffers: depends on UniformBlocks and SharedStorageBlocks being set by the linker. For the regular GLSL code path, those datastructures are filled earlier. For NIR linking code path we need to generate the nir_shader first then process it -- and currently the processing works with all shaders together. So move the passes out of brw_create_nir into its own function, called by the brwProgramStringNotify and brw_link_shader(). This patch prepares ground for ARB_gl_spirv, that will make use of NIR linker. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl/nir: Fix copying 64-bit values in uniform storageCaio Marcelo de Oliveira Filho2019-06-241-1/+1
| | | | | | | | | | | The iterator `i` already walks the right amount now that is incremented by `dmul`, so no need to `* 2`. Fixes invalid memory access in upcoming ARB_gl_spirv tests. Failure bisected by Arcady Goldmints-Orlov. Fixes: b019fe8a5b6 "glsl/nir: Fix handling of 64-bit values in uniform storage" Reviewed-by: Jason Ekstrand <[email protected]>
* glsl/nir: Fix copying vector constant valuesCaio Marcelo de Oliveira Filho2019-06-241-1/+1
| | | | | | | | | | For n_columns == 1, we have a vector which is handled by the else case. Fixes invalid memory access in upcoming ARB_gl_spirv tests. Failure bisected by Arcady Goldmints-Orlov. Fixes: 81e51b412e9 "nir: Make nir_constant a vector rather than a matrix" Reviewed-by: Jason Ekstrand <[email protected]>
* amd/common: lower bitfield_extract to ubfe/ibfe.Daniel Schürmann2019-06-244-35/+22
| | | | Reviewed-by: Connor Abbott <[email protected]>
* amd/common: lower bitfield_insert to bfm & bitfield_selectDaniel Schürmann2019-06-243-26/+27
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: introduce lowering of bitfield_insert to bfm and a new opcode ↵Daniel Schürmann2019-06-243-0/+11
| | | | | | | | | | bitfield_select. bitfield_select is defined as: bitfield_select(mask, base, insert) = (mask & base) | (~mask & insert) matching the behavior of AMD's BFI instruction. Reviewed-by: Connor Abbott <[email protected]>
* nir/algebraic: Use unsigned comparison when lowering bitfield insert/extractDaniel Schürmann2019-06-241-2/+2
| | | | | | | | This lets us use the optimization pattern (('ult', 31, ('iand', b, 31)), False) to remove the bcsel instruction for code originating in D3D shaders. Reviewed-by: Connor Abbott <[email protected]>
* nir/algebraic: Remove unnecessary iand of [iu]bfe and bfm sourcesDaniel Schürmann2019-06-241-0/+8
| | | | | | | | The [iu]bfe and bfm instructions are defined to only use the five least significant bits. This optimizes a common pattern from D3D -> SPIR-V translation. Reviewed-by: Connor Abbott <[email protected]>
* nir: define behavior of nir_op_bfm and nir_op_u/ibfe according to SM5 spec.Daniel Schürmann2019-06-246-35/+18
| | | | | | | | | | | That is: the five least significant bits provide the values of 'bits' and 'offset' which is the case for all hardware currently supported by NIR and using the bfm/bfe instructions. This patch also changes the lowering of bitfield_insert/extract using shifts to not use bfm and removes the flag 'lower_bfm'. Tested-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/algebraic: add optimization pattern for ('ult', a, ('and', b, a)) and ↵Daniel Schürmann2019-06-241-0/+4
| | | | | | | | | | | friends. These optimizations are based on the fact that 'and(a,b) <= umin(a,b)'. For AMD, this series moves the optimization from LLVM to NIR, so currently no vkpipeline-db changes here. Reviewed-by: Ian Romanick <[email protected]>
* lima/ppir: Add fsat opAndreas Baierl2019-06-244-0/+20
| | | | | Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: Add fneg opAndreas Baierl2019-06-244-0/+19
| | | | | Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: Add fabs opAndreas Baierl2019-06-244-0/+20
| | | | | Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* util: support "y" and "n" in env_var_as_boolean()Eric Engestrom2019-06-241-0/+2
| | | | | | | Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* lima/ppir: lower ffma in ppirAndreas Baierl2019-06-241-0/+1
| | | | | | | Since we cannot handle ffma in ppir, lower it on nir level already. Signed-off-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* radv: add support for VK_AMD_buffer_markerSamuel Pitoiset2019-06-242-0/+36
| | | | | | | | This simple extension might be useful for debugging purposes. GAPID has support for it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: error out if platforms contains empty stringTapani Pälli2019-06-241-0/+4
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110939 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* anv: Add HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED in vk_formatNataraj Deshpande2019-06-243-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | When HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED is used, then the platform gralloc module will select a format based on the usage flags provided by the camera device and the other endpoint of the stream. The patch fixes crash in vulkan when the test is run with camera stream set to HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED. Test: android.graphics.cts.CameraVulkanGpuTest#testCameraImportAndRendering on chromebook with camera HAL3. v2: use AHARDWAREBUFFER_FORMAT_IMPLEMENTATION_DEFINED and take AHARDWAREBUFFER_USAGE_CAMERA_MASK in to account (Gurchetan) Fixes: f1654fa7e31 "anv/android: support creating images from external format" Signed-off-by: Nataraj Deshpande <[email protected]> Signed-off-by: Gurchetan Singh <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
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