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* amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu2017-03-301-12/+33
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* amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle2017-03-301-2/+2
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-303-3/+9
| | | | | 1) dccCompatible for padding MSAA surface to support fast clear 2) dccPipeWorkaround for padding surface to support dcc
* amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not ↵Nicolai Hähnle2017-03-302-0/+18
| | | | calculated correctly
* amdgpu/addrlib: Add a new output flag to notify client that the returned ↵Nicolai Hähnle2017-03-302-1/+5
| | | | | | | tile index is for PRT on SI If this flag is set for mip0, client should set prt flag for sub mips, so that address lib can select the correct tile index for sub mips.
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-304-20/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | The usage should be client first call AddrComputeSurfaceInfo() on depth surface with flag "matchStencilTilecfg", AddrLib will use 2DThin1 tile index for depth as much as possible and do not down grade unless alignment requirement cannot be met. 1. If there is a matched 2DThin1 tile index for stencil which make sure they will share same tile config parameters, then return the stencil 2DThin1 tile index as well. 2. If using 2DThin1 tile mode cannot make sure such thing happen, and TcCompatible flag was set, then ignore this flag then try 2DThin1 tile mode for depth and stencil again. 3. If 2DThin1 tile mode cannot make sure depth and stencil to have same tile config parameters, then down grade depth surface tile mode to 1DThin1. 4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile index for stencil. 5. If depth surface's tile mode is PRT, then return invalid tile index to stencil since their tile config parameters will never be met. Client driver then check the returned tile index of stencil -- if it is not invalid tile index, then call AddrComputeSurfaceInfo() on stencil surface with the returned stencil tile index to get full output information. Please note, client needs to set flag "useTileIndex" when AddrLib get created.
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ↵Frans Gu2017-03-304-91/+282
| | | | | | | | ratio settings By this way, we can have valid equation for 2D_THIN1 tile mode. Add flag "preferEquation" to return equation index without adjusting input tile mode.
* amdgpu/addrlib: do some tile mode conversions to display surfaceFrans Gu2017-03-301-2/+3
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* amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang2017-03-306-92/+56
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* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-309-157/+401
| | | | | | | | | 1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger than 1D 2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than requested alignment. Also, related changes to tile mode optimization for needEquation.
* amdgpu/addrlib: Always returns pixelPitch in original pixelsXavi Zhang2017-03-301-14/+10
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* amdgpu/addrlib: fix crash on allocation failureSabre Shao2017-03-305-36/+31
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* amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu2017-03-303-4/+28
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* amdgpu/addrlib: support non-power2 height alignment (for linear surface)Roy Zhan2017-03-301-1/+10
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* amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu2017-03-301-0/+2
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* amdgpu/addrlib: style cleanupNicolai Hähnle2017-03-302-28/+15
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-308-49/+131
| | | | | The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment.
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-308-66/+66
| | | | | | Find ^/{80,99}$ and replace them to 100 "/" Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-3013-73/+68
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-3016-892/+969
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-3018-895/+895
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-308-14/+211
| | | | | This can be used by address lib client to ask address lib to select tile mode.
* amdgpu/addrlib: Stylish cleanup.Xavi Zhang2017-03-305-17/+16
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
| | | | Experiment show 1D tiling + TcCompatible cannot work together.
* amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang2017-03-301-4/+4
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* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-303-14/+21
| | | | | This is useful for debugging and special cases for stencil surfaces do not require texture fetch compatible.
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-3012-118/+1344
| | | | | | | | | | | | | | | | 1. Add new surface flags needEquation for client driver use to force the surface tile setting equation compatible. Override 2D/3D macro tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1. 2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure to return number of equations and the equation table to client driver 3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to return the equation index to client driver Please note the use of address equation has following restrictions: 1) The surface can't be splitable 2) The surface can't have non zero tile swizzle value 3) Surface with > 1 slices must have PRT tile mode, which disable slice rotation
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-305-32/+32
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* amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2017-03-302-6/+6
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* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-304-0/+115
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* amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan2017-03-301-8/+20
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* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
| | | | | | | | Sometimes client driver passes valid tile info into address library, in this case, the tile index is computed in function HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg. We need to call HwlPostCheckTileIndex to calculate the correct tile index to get tile split bytes for this case.
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-303-10/+20
| | | | It helps fix analysis warnings in MSC.
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-305-13/+80
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* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
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* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex ↵Nicolai Hähnle2017-03-307-32/+53
| | | | | | | | | | | and AddrConvertTileInfoToHW When clients queries tile Info from tile index and expects accurate tileSplit info, bits per pixel info is required to be provided since this is necessary for computing tileSplitBytes; otherwise Addrlib will return value of "tileBytes" instead if bpp is 0 - which is also current logic. If clients don't need tileSplit info, it's OK to pass bpp with value 0.
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-302-51/+19
| | | | | Switch the tile index based on logic instead of hardcoded threshold for different ASIC.
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-302-1/+7
| | | | | This flag indicates to the client if this level's DCC memory is aligned or not. No aligned means there are padding to the end.
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
| | | | | | Add one more abstraction layer into inheritance system. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-305-3528/+3595
| | | | | | No code changes. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
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* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
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* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
| | | | | | | | Kaveri (2-pipe) macro tiling mode table was initially set to all 4-aspect-ratio so the swizzling path did not work for it and then we chose to pad the offset. We now discover the root cause is that if ratio > 2, the swizzling path does not work. So we can safely use the same path for Kaveri.
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-307-34/+57
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
| | | | | | | Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
| | | | | Flag tcCompatible has different usage in CI and VI. Add a new flag "nonSplit" for CI.
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
| | | | | | | Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp depth surface. Remove the sanity check that tileSplitBytes must be greater than row size. There could be performance loss but may be covered by non-split depth which enables tc-compatible read.
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