summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* i965/vec4: Init mlen for several send from GRF instructions.Francisco Jerez2015-02-103-5/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't infer MRF dependencies for send from GRF instructions.Francisco Jerez2015-02-101-14/+18
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix the scheduler to take into account reads and writes of ↵Francisco Jerez2015-02-103-5/+29
| | | | | | | | multiple registers. v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends ↵Francisco Jerez2015-02-101-1/+1
| | | | | | from GRF. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Pass dst register to the vec4_instruction constructor.Francisco Jerez2015-02-101-7/+5
| | | | | | So regs_written gets initialized with a sensible value. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.Francisco Jerez2015-02-101-0/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Implement equals() method for dst_reg too.Francisco Jerez2015-02-102-0/+18
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.Francisco Jerez2015-02-101-1/+2
| | | | | | | | | | | Scalar registers are required to have zero stride, fix the regs_written calculation not to assume that the instruction writes zero registers in that case. v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Fix stack allocation of fs_inst and stop stealing src array ↵Francisco Jerez2015-02-102-37/+39
| | | | | | | | | | provided on construction. Using 'ralloc*(this, ...)' is wrong if the object has automatic storage or was allocated through any other means. Use normal dynamic memory instead. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove duplicate include of brw_shader.hFrancisco Jerez2015-02-101-1/+0
| | | | | | | The second one was inside an extern "C" block, luckily it was being discarded by the preprocessor. Reviewed-by: Matt Turner <[email protected]>
* i965: Move up fs_inst::flag_subreg to backend_instruction.Francisco Jerez2015-02-105-7/+16
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Move up fs_inst::regs_written to backend_instruction.Francisco Jerez2015-02-103-1/+2
| | | | | | It will also be useful in the VEC4 back-end. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove dependency of vec4_instruction on the visitor class.Francisco Jerez2015-02-103-36/+32
| | | | | | | | | The only reason why you need a vec4_visitor to construct a vec4_instruction is to initialize vec4_instruction::ir and ::annotation. Instead set them from vec4_visitor::emit() just like fs_visitor does. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dependency of fs_inst on the visitor class.Francisco Jerez2015-02-107-13/+12
| | | | | | The fs_visitor argument of fs_inst::regs_read() wasn't used at all. Reviewed-by: Matt Turner <[email protected]>
* i965: Move IR object definitions to separate header files.Francisco Jerez2015-02-104-381/+450
| | | | | | | | | | | | One should be able to manipulate i965 IR without pulling the whole FS/VEC4 visitor classes -- Optimization passes and other transformations would ideally be visitor-agnostic. Among other issues this avoids a circular dependency between the header file where such visitor-agnostic code will be defined and the main FS/VEC4 header where both IR (layer below) and visitor (layer above) happen to be defined. Reviewed-by: Matt Turner <[email protected]>
* i965: Factor out virtual GRF allocation to a separate object.Francisco Jerez2015-02-1018-201/+235
| | | | | | | | | | | | | Right now virtual GRF book-keeping and allocation is performed in each visitor class separately (among other hundred different things), leading to duplicated logic in each visitor and preventing layering as it forces any code that manipulates i965 IR and needs to allocate virtual registers to depend on the specific visitor that happens to be used to translate from GLSL IR. v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor). Reviewed-by: Matt Turner <[email protected]>
* glsl: Forbid calling the constructor of any opaque type.Francisco Jerez2015-02-101-3/+3
| | | | | | The spec doesn't define any opaque type constructors. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Return correct number of coordinate components for cubemap array images.Francisco Jerez2015-02-101-2/+7
| | | | | | | | | Cubemap array images are unlike cubemap array samplers in that they don't need an additional coordinate to index individual cubemaps in the array, instead they behave like a 2D array of 6n layers, with n the number of cubemaps in the array. Take this exception into account. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Bump MAX_IMAGE_UNIFORMS to 32.Francisco Jerez2015-02-101-1/+1
| | | | | | So the i965 driver can expose 32 image uniforms per shader stage. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename the CEILING() macro to DIV_ROUND_UP().Francisco Jerez2015-02-103-3/+3
| | | | | | | | | | Some people have complained that code using the CEILING() macro is difficult to understand because it's not immediately obvious what it is supposed to do until you go and look up its definition. Use a more descriptive name that matches the similar utility macro in the Linux kernel. Reviewed-by: Matt Turner <[email protected]>
* nv50,nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediatelyTiziano Bacocco2015-02-102-0/+6
| | | | | | | | | Without this when an application issues that query, it would try to wait the result from the gpu, and since no query has been actually issued, it will wait forever. Signed-off-by: Tiziano Bacocco <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Fold IMM into MADRoy Spliet2015-02-101-0/+53
| | | | | | | | | | | | | Add a specific optimisation pass for NV50 to check whether SRC0 or SRC1 is a MOV dst, IMM. If so: fold the IMM in and try to drop the MOV. Must be done post-RA because it requires that SDST == SSRC2. V2: improve readability and add comments to clarify decisions V3: Remove redundant code... compiler already attempts to put the IMM in SSRC1 Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add emit support for MAD IMM formatRoy Spliet2015-02-101-0/+8
| | | | | | | | | But don't enable generation of it in the opProperties, because we can't guarantee the SDST==SRC2 constraint until after register assignment. We'll add a post-RA folding pass to utilise this. Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add support for MAD 4-byte opcodeRoy Spliet2015-02-102-8/+6
| | | | | | | | | | | | Add emission rules for negative and saturate flags for MAD 4-byte opcodes, and get rid of some of the constraints. Obviously tested with a wide variety of shaders. V2: Document MAD as supported short form V3: Split up IMM from short-form modifiers Signed-off-by: Roy Spliet <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: change the way float face is returnedIlia Mirkin2015-02-102-4/+6
| | | | | | | | | | | | The old way made it impossible for the optimizer to reason about what was going on. The new way is the same number of instructions (the neg gets folded into the cvt) but enables the optimizer to be cleverer if comparing to a constant (most common case). [The optimizer is presently not sufficiently clever to work this out, but it could relatively easily be made to be. The old way would have required significant complexity to work out.] Signed-off-by: Ilia Mirkin <[email protected]>
* nir: Mark nir_print_instr's instr pointer as const.Kenneth Graunke2015-02-102-3/+3
| | | | | | | | Printing instructions doesn't modify them, so we can mark the parameter const. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix integer border color on Haswell.Kenneth Graunke2015-02-093-0/+66
| | | | | | | | | +82 Piglits - 100% of border color tests now pass on Haswell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* i965: Use a gl_color_union for sampler border color.Kenneth Graunke2015-02-091-53/+52
| | | | | | | | | | | This should have no effect, but will make it easier to implement other bug fixes. v2: Eliminate "unsigned one" local; just use the value where necessary. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: [email protected]
* i965: Override swizzles for integer luminance formats.Kenneth Graunke2015-02-091-0/+8
| | | | | | | | | | | | | | | The hardware's integer luminance formats are completely unusable; currently we fall back to RGBA. This means we need to override the texture swizzle to obtain the XXX1 values expected for luminance formats. Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled] on Broadwell - 100% of border color tests now pass on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* util/u_atomic: Add new macro p_atomic_addCarl Worth2015-02-092-0/+21
| | | | | | | | | | | | | This provides for atomic addition, which will be used by an upcoming shader-cache patch. A simple test is added to "make check" as well. Note: The various O/S functions differ on whether they return the original value or the value after the addition, so I did not provide an add_return() macro which would be sensitive to that difference. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Aaron Watry <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* util/hash_table: Try to hit a double-insertion bug in the collision testJason Ekstrand2015-02-071-1/+13
| | | | Reviewed-by: Eric Anholt <[email protected]>
* util/set: Do a full search when adding new itemsJason Ekstrand2015-02-071-6/+15
| | | | | | | | | | | | Previously, the set_insert function would bail early if it found a deleted slot that it could re-use. However, this is a problem if the key being inserted is already in the set but further down the list. If this happens, the element ends up getting inserted in the set twice. This commit makes it so that we walk over all of the possible entries for the given key and then, if we don't find the key, place it in the available free entry we found. Reviewed-by: Eric Anholt <[email protected]>
* util/hash_table: Do a full search when adding new itemsJason Ekstrand2015-02-071-7/+16
| | | | | | | | | | | | Previously, the hash_table_insert function would bail early if it found a deleted slot that it could re-use. However, this is a problem if the key being inserted is already in the hash table but further down the list. If this happens, the element ends up getting inserted in the hash table twice. This commit makes it so that we walk over all of the possible entries for the given key and then, if we don't find the key, place it in the available free entry we found. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Make renderbuffer FBO attachments not layeredJames Legg2015-02-081-0/+1
| | | | | | | | | | | | For framebuffer completeness checks, consider renderbuffers as not layered. Previously, they would have counted as layered if a layered textured had previously been bound to the same attachment point. This could cause framebuffer completeness checks to incorrectly fail with GL_FRAMEBUFFER_INCOMPLETE_LAYER_TARGETS, even if no layered attachments were present. Reviewed-by: Chris Forbes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89026
* Post-branch version bump to 10.6.0-devel, add release notes templateEmil Velikov2015-02-072-1/+59
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallium/hud: also try R8_UNORM format for font texture10.5-branchpointBrian Paul2015-02-071-9/+15
| | | | | | | Convert the code to try formats from an array rather than a bunch of if/else cases. Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: flush stdout in print_help(), for WindowsBrian Paul2015-02-071-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965: Add more stringent blitter assertionsBen Widawsky2015-02-071-0/+3
| | | | | | | | | | | | Blits to or from a y-tiled surface must always be a multiple of the tile size. From page 16 of the HSW PRM (https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16) "The pitch of a tiled enclosing region must be an integral number of tile widths" Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Consolidate some of the intel_blit logicBen Widawsky2015-02-071-20/+8
| | | | | | | | | | | An upcoming patch is going to introduce some code here, and having this code organized as the patch does makes it a bit easier to read later. There should be no functional change here. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* st/dri: Make depth buffer optional for postprocessingPark, Jeongmin2015-02-072-2/+2
| | | | | | Since only pp_jimenezmlaa uses depth buffer, we can make it optional. Signed-off-by: Marek Olšák <[email protected]>
* postprocess: Check for depth buffer in pp_jimenezmlaaPark, Jeongmin2015-02-071-0/+3
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88962 Signed-off-by: Marek Olšák <[email protected]>
* i965/vec4: Correct MUL destination hazardBen Widawsky2015-02-061-4/+4
| | | | | | | | | | | | | | | | | | | | | | As it turns out, we were over-thinking the cause of the hang on Cherryview. It's simply errata for Cherryview. commit 88fea85f09e2252035bec66ab26c375b45b000f5 Author: Ben Widawsky <[email protected]> Date: Fri Nov 21 10:47:41 2014 -0800 i965/vec4/gen8: Handle the MUL dest hazard exception This is an explanation to why we never saw the hang on BDW. NOTE: The problem the original patch was trying to fix does still exist. It will have to be fixed at some point. v2: Modify commit message, s/CHV/BDW Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212 Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* docs: add news item and link release notes for mesa 10.4.4Emil Velikov2015-02-072-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add sha256 sums for the 10.4.4 releaseEmil Velikov2015-02-071-1/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 54da987baec25fbaf6975c93f197ddbfe65a303c)
* Add release notes for the 10.4.4 releaseEmil Velikov2015-02-071-0/+98
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 62eb27ac8bbd979796f50e253f6c786d7d791242)
* nir: Fix broken fsat recognizer.Eric Anholt2015-02-061-1/+1
| | | | | | | | We've probably never seen this ridiculous pattern in the wild, so it didn't matter. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Slightly simplify algebraic code generation by reusing a struct.Eric Anholt2015-02-061-6/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* tgsi/ureg: Add missing some missing opcodes opcode_tmp.hEric Anholt2015-02-061-0/+4
| | | | | | I wanted all of these for NIR-to-TGSI. Reviewed-by: Roland Scheidegger <[email protected]>
* tgsi/ureg: Move ureg_dst_register() to the header.Eric Anholt2015-02-062-28/+25
| | | | | | | I wanted to use it for nir-to-tgsi. The equivalent ureg_src_register() is also located here. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/u_tests: test a NULL buffer sampler viewMarek Olšák2015-02-062-13/+42
| | | | Reviewed-by: Glenn Kennard <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 17:10:17 +0000