summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* FINISHME: anv: Fix VkPhysicalDeviceExternalImageFormatInfo for ↵chadv/review/anv-drm-format-mod/2019-07-26-r1Chad Versace2019-07-261-0/+3
| | | | VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
* RFC: anv: Advertise VK_EXT_image_drm_format_modifierChad Versace2019-07-261-0/+1
|
* FINISHME: anv: vkGetImageSubresourceLayout for ↵Chad Versace2019-07-261-0/+7
| | | | VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
* FINISHME: anv: Support VkImageDrmFormatModifierExplicitCreateInfoEXTChad Versace2019-07-261-0/+8
|
* RFC: anv: Support VkImageDrmFormatModifierListCreateInfoEXTChad Versace2019-07-261-0/+9
|
* RFC: anv: Implement VkPhysicalDeviceImageDrmFormatModifierInfoEXTChad Versace2019-07-261-6/+27
|
* anv: Rename param anv_get_image_format_properties()::infoChad Versace2019-07-261-18/+18
| | | | | Rename it to 'base_info', to distinguish it from 'drm_info' introduced in upcoming commit.
* RFC: anv: Implement VkDrmFormatModifierPropertiesListEXTChad Versace2019-07-261-36/+152
|
* anv: Reject linear depth/stencil in anv_get_format_plane()Chad Versace2019-07-261-0/+4
| | | | | | anv_get_image_format_features() already reports that we do not support linear images with depth/stencil formats. For consistency, teach anv_get_format_plane() to do the same.
* anv: Refactor struct anv_image_create_infoChad Versace2019-07-264-13/+13
| | | | | | | | | | Replace field 'isl_tiling_flags' with 'drm_format_mod'. This cleanup makes the override features of anv_image_create_info behave more similarly to VkImageDrmFormatModifierExplicitCreateInfoEXT. The field 'isl_tiling_flags' offered more flexibility than needed. The driver set at most one flag, and when set the driver translated the sole flag into a DRM format modifier.
* anv: Define struct anv_tilingChad Versace2019-07-268-50/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor only. No intended behavioral change. Much of the existing code assumes, with good justification, that tiling is either VK_IMAGE_TILING_LINEAR or VK_IMAGE_TILING_OPTIMAL. But VK_EXT_image_drm_format_modifier will void that assumption. Some examples where currently valid assumptions become invalid: - Code written as if (tiling != VK_IMAGE_TILING_OPTIMAL) but whose true intent is if (tiling == VK_IMAGE_TILING_LINEAR) will break when tiling is VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT. - Some code written as if (tilng == VK_IMAGE_TILING_LINEAR) will need updating to if (tiling == VK_IMAGE_TILING_LINEAR || (tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT && drm_format_mod == DRM_FORMAT_MOD_LINEAR)) - Many query functions with a VkImageTiling parameter will require an additional parameter for the DRM format modifier. The invalidity of many of the above cases become clearer if we generally abandon using VkImageTiling to indicate tiling, and instead use a new type that includes an optional DRM format modifier: struct anv_tiling { VkImageTiling vk; uint64_t drm_format_mod; }; This patch does not attempt to fix code with soon-to-be invalid assumptions. Instead, it restricts itself to the following changes: - Replace type of: - anv_get_format_features()::tiling - anv_get_format_plane()::tiling - anv_get_isl_format()::tiling - anv_image::tiling - Fold anv_image::drm_format_mod into anv_image::tiling. - Replace variables 'vk_tiling' with 'tiling.vk'.
* anv: Include drm_fourcc.h in anv_private.hChad Versace2019-07-264-3/+1
| | | | | To allow use of DRM_FORMAT_MOD_INVALID in future inline functions for struct anv_tiling.
* anv: Implement VK_EXT_subgroup_size_controlJason Ekstrand2019-07-243-2/+46
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv/pipeline: Plumb pipeline shader stage create flagsJason Ekstrand2019-07-241-12/+21
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/compiler: Allow for required subgroup sizesJason Ekstrand2019-07-243-6/+42
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/compiler: Allow for varying subgroup sizesJason Ekstrand2019-07-243-2/+26
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir/lower_subgroups: Properly lower masks when subgroup_size == 0Jason Ekstrand2019-07-241-5/+11
| | | | | | | | | | | | Instead of building a constant mask (which depends on knowing the subgroup size), we build an expression. Because the pass uses the nir_shader_lower_instructions helper, subgroup lowering will be run on any newly emitted instructions as well as the previously existing instructions. In particular, if the subgroup size is known, the newly emitted subgroup_size intrinsic will get turned into a constant and a later constant folding pass will clean it up. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* vulkan: Update the XML and headers to 1.1.116Jason Ekstrand2019-07-242-47/+125
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/compiler: Be more conservative about subgroup sizes in GLJason Ekstrand2019-07-2411-13/+55
| | | | | | | | | | | The rules for gl_SubgroupSize in Vulkan require that it be a constant that can be queried through the API. However, all GL requires is that it's a uniform. Instead of always claiming that the subgroup size in the shader is 32 in GL like we have to do for Vulkan, claim 8 for geometry stages, the maximum for fragment shaders, and the actual size for compute. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/compiler: Lower gl_SubgroupSize in postprocess_nirJason Ekstrand2019-07-241-2/+7
| | | | | | | | | | Instead of lowering the subgroup size so early, wait until we have more information. In particular, we're going to want different subgroup sizes from different stages depending on the API. We also defer lowering of subgroup masks because the ge/gt masks require the subgroup size to generate a subgroup mask. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/nir: Make brw_nir_apply_sampler_key more genericJason Ekstrand2019-07-247-16/+26
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: Add lowering for nir_op_irem and nir_op_imodSagar Ghuge2019-07-241-2/+16
| | | | | | | | | | Tested on Gen > 9. v2: 1) Fix lowering 2) Keep a consistent i/u order (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* main: Fix memleaks in mesa_use_programYevhenii Kolesnikov2019-07-241-0/+2
| | | | | | | | | Add freeing of SubroutineIndexes to the _mesa_free_shader_state. Fixes: 4566aaaa5b1 ("mesa/subroutines: start adding per-context subroutine index support (v1.1)") Signed-off-by: Yevhenii Kolesnikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* intel/compiler: don't use a keyword struct for a class fs_regAndrii Simiklit2019-07-241-1/+1
| | | | | | | | warning: struct 'fs_reg' was previously declared as a class Fixes: e64be391 ("intel/compiler: generalize the combine constants pass") Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Andrii Simiklit <[email protected]>
* lima/ppir: fix disassembler temp read/write printQiang Yu2019-07-241-9/+23
| | | | | | | | temp read/write use negtive offset, and handle alignment==1 case. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
* gallium+mesa: fix tgsi_semantic array typeEric Engestrom2019-07-244-10/+16
| | | | | | Fixes: ed23335a313dfc9cec26 ("gallium: use enums in p_shader_tokens.h (v2)") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* util: fix no-op macro (bad number of arguments)Eric Engestrom2019-07-241-1/+1
| | | | | | Fixes: b8e077daee4d6369d774 ("util: no-op __builtin_types_compatible_p() for non-GCC compilers") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radv/gfx10: enable VK_EXT_transform_feedbackSamuel Pitoiset2019-07-241-1/+1
| | | | | | | | | | | | When a pipeline uses transform feedback, the driver fallbacks to the legacy path because NGG support for streamout is a non-trivial amount of work. AMDVLK also uses the legacy path for streamout, while RadeonSI uses the new NGG path. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: do not enable NGG if a pipeline uses XFBSamuel Pitoiset2019-07-241-0/+27
| | | | | | | | NGG GS for streamout requires a bunch of work, so enable it with the legacy path only for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: emit streamout shader configSamuel Pitoiset2019-07-241-7/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: declare streamout user SGPRsSamuel Pitoiset2019-07-241-3/+0
| | | | | | | Required for legacy streamout. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: update streamout descriptorsSamuel Pitoiset2019-07-241-2/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: fix VS input VGPRs with the legacy pathSamuel Pitoiset2019-07-242-5/+15
| | | | | | | For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallivm: rework lp_build_tgsi_soa to take a structDave Airlie2019-07-245-114/+126
| | | | | | | The parameters were getting messy and I have to add a few more for compute shaders, so clean it up before proceeding. Reviewed-by: Roland Scheidegger <[email protected]>
* nir/lower_io: Return SSA defs from helpersJason Ekstrand2019-07-231-25/+42
| | | | | | | | I can't find a single place where nir_lower_io is called after going out of SSA which is the only real reason why you wouldn't do this. Returning SSA defs is more idiomatic and is required for the next commit. Reviewed-by: Matt Turner <[email protected]>
* meson: allow building all glx without any driversDylan Baker2019-07-232-7/+5
| | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111016 Fixes: a47c525f3281a2753180e076c7e9b7772aff8f06 ("meson: build glx") Acked-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* swr/rasterizer: Fix 3D resource copies.Jan Zielinski2019-07-231-0/+14
| | | | | | Ensure constant attributes stay constant with barycentric interpolation. Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: Fix return type on SIMD8 version of Clamp and Normalize ↵Jan Zielinski2019-07-231-2/+2
| | | | | | utility functions Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: small formatting changesJan Zielinski2019-07-233-22/+48
| | | | Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: Adding support for unhandled clipEnable stateJan Zielinski2019-07-233-4/+8
| | | | | | Clipping is not correctly handled by the rasterizer - fixing this. Reviewed-by: Alok Hota <[email protected]>
* radv/gfx10: Enable binning.Bas Nieuwenhuizen2019-07-231-2/+1
| | | | | | | | | | Numbers for Talos: gfx10 without binning: 77.0 77.7 77.2 77.6 gfx10 with binning: 82.3 82.0 82.7 82.4 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx10: Implement bin size calculation.Bas Nieuwenhuizen2019-07-231-2/+112
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/gfx9: Select between depth/color bins based on area.Bas Nieuwenhuizen2019-07-231-2/+2
| | | | | | | Mirrors radeonsi. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Generalize binning settings.Bas Nieuwenhuizen2019-07-231-10/+2
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx10: Use new scan converter.Bas Nieuwenhuizen2019-07-231-9/+51
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Set FLUSH_ON_BINNING_TRANSITION.Bas Nieuwenhuizen2019-07-233-10/+50
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Use pbb_allow for framebuffer BREAK_BATCH.Bas Nieuwenhuizen2019-07-231-1/+1
| | | | | | | Ported from radeonsi. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.Marek Olšák2019-07-231-5/+23
| | | | | | This doesn't implement the color buffer load. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* tgsi/scan: add uses_fbfetchMarek Olšák2019-07-233-1/+5
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: fail if importing a texture with incorrect last_level or samplesMarek Olšák2019-07-231-5/+38
| | | | | | v2: don't fail if the texture comes from an incompatible driver. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> (v1)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 04:35:16 +0000