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* radeonsi/gfx9: set the LLVM processor, require LLVM 5.0Marek Olšák2017-03-302-0/+9
* radeonsi/gfx9: add GFX9 and VEGA10 enumsMarek Olšák2017-03-304-5/+15
* amd: GFX9 packet changesMarek Olšák2017-03-304-13/+26
* amd: define event types for GFX9Marek Olšák2017-03-301-0/+54
* amd: add texture format definitions for GFX9Marek Olšák2017-03-305-27/+152
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-305-66/+66
* amd: normalize register definition formattingMarek Olšák2017-03-303-92/+174
* amd: import GFX9 register definitionsMarek Olšák2017-03-302-0/+7287
* radeonsi: code shuffling in si_init_depth_surfaceMarek Olšák2017-03-301-54/+32
* amd/addrlib: silence warningsMarek Olšák2017-03-304-15/+15
* amd/addrlib: import gfx9 supportNicolai Hähnle2017-03-3019-3/+22053
* amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to diffe...Kevin Furrow2017-03-303-19/+45
* amd/addrlib: Fix selection of swizzle modes for 3D compressed images.Kevin Furrow2017-03-301-1/+2
* amd/addrlib: Add support for ETC2 and ASTC formats.Kevin Furrow2017-03-303-1/+119
* amd/addrlib: Bump version to 6.02Joe Ma2017-03-301-1/+1
* amd/addrlib: Adjust slie size after pitch and actual height adjustmentFrans Gu2017-03-301-26/+31
* amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu2017-03-301-12/+33
* amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle2017-03-301-2/+2
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-303-3/+9
* amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calcu...Nicolai Hähnle2017-03-302-0/+18
* amdgpu/addrlib: Add a new output flag to notify client that the returned tile...Nicolai Hähnle2017-03-302-1/+5
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-304-20/+152
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu2017-03-304-91/+282
* amdgpu/addrlib: do some tile mode conversions to display surfaceFrans Gu2017-03-301-2/+3
* amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang2017-03-306-92/+56
* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-309-157/+401
* amdgpu/addrlib: Always returns pixelPitch in original pixelsXavi Zhang2017-03-301-14/+10
* amdgpu/addrlib: fix crash on allocation failureSabre Shao2017-03-305-36/+31
* amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu2017-03-303-4/+28
* amdgpu/addrlib: support non-power2 height alignment (for linear surface)Roy Zhan2017-03-301-1/+10
* amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu2017-03-301-0/+2
* amdgpu/addrlib: style cleanupNicolai Hähnle2017-03-302-28/+15
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-308-49/+131
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-308-66/+66
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-3013-73/+68
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-3016-892/+969
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-3018-895/+895
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-308-14/+211
* amdgpu/addrlib: Stylish cleanup.Xavi Zhang2017-03-305-17/+16
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
* amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang2017-03-301-4/+4
* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-303-14/+21
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-3012-118/+1344
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-305-32/+32
* amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2017-03-302-6/+6
* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-304-0/+115
* amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan2017-03-301-8/+20
* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-303-10/+20
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-305-13/+80
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