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* intel/compiler: Change src1 reg type to unsigned doublewordSagar Ghuge2018-10-232-3/+3
| | | | | | | | | | | To have uniform behavior while disassembling send(c) instruction use register type of unsigned doubleword for src1 when message descriptor is immediate value. Bspec does not specifiy anything for src1 immediate default type. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* mesa/glformats: Remove redundant helper _mesa_base_format_component_countEduardo Lima Mitev2018-10-234-33/+3
| | | | | | | There exists _mesa_components_in_format() which already includes all cases handled in _mesa_base_format_component_count(). Reviewed-by: Tapani Pälli <[email protected]>
* nir/algebraic: Fix a typo in the bit size validation codeJason Ekstrand2018-10-231-2/+2
| | | | | | | | The conon_bit_class and canon_var_class variables got switched. Fixes: 932c650e0b "nir/algebraic: Loosen a restriction on variables" Reported-by: Ian Romanick <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* amd/common: check DRM version 3.27 for JPEG decodeLeo Liu2018-10-231-1/+1
| | | | | | | | | | JPEG was added after DRM version 3.26 Signed-off-by: Leo Liu <[email protected]> Fixes: 4558758c51749(amd/common: add vcn jpeg ip info query) Cc: Boyuan Zhang <[email protected]> Cc: Alex Smith <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* docs: update calendarJuan A. Suarez Romero2018-10-231-2/+2
| | | | | | | | I'll take care of 18.2 releases series on Andres behalf. CC: Andres Gomez <[email protected]> CC: Dylan Baker <[email protected]> CC: Emil Velikov <[email protected]>
* intel/decoders: fix end of batch limitLionel Landwerlin2018-10-233-9/+10
| | | | | | | | | | | | | Pointer arithmetic... v2: s/4/sizeof(uint32_t)/ (Eric) v3: Give bytes to print_batch() in error_decode (Lionel) Make clear what values we're dealing with in error_decode (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (v2) Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: enable vcn jpeg decode for ravenBoyuan Zhang2018-10-231-0/+2
| | | | | | | Enable vcn jpeg decode for raven. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* winsys/amdgpu: add vcn jpeg cs supportBoyuan Zhang2018-10-231-0/+12
| | | | | | | Add vcn jpeg cs support, align cs by no-op. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* amd/common: add vcn jpeg ip info queryBoyuan Zhang2018-10-231-2/+12
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg target buffer cmdBoyuan Zhang2018-10-231-1/+72
| | | | | | | | Implement jpeg target buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg bitstream buffer cmdBoyuan Zhang2018-10-231-1/+45
| | | | | | | | Implement jpeg bitstream buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/uvd: remove get mjpeg slice headerBoyuan Zhang2018-10-231-157/+0
| | | | | | | | Move the previous get_mjpeg_slice_heaeder function and eoi from "radeon/vcn" to "st/va". Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/va: get mjpeg slice headerBoyuan Zhang2018-10-233-2/+164
| | | | | | | | Move the previous get_mjpeg_slice_heaeder function and eoi from "radeon/vcn" to "st/va". Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add jpeg decode implementationBoyuan Zhang2018-10-235-7/+119
| | | | | | | | Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg specific cmd sending function in end_frame call. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: separate send cmd call from end frameBoyuan Zhang2018-10-232-8/+28
| | | | | | | | Use function pointer for sending cmd in end_frame call. By doing this, we can assign different cmd sending logics for Jpeg decode later. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: create cs based on ring typeBoyuan Zhang2018-10-231-2/+6
| | | | | | | Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/winsys: add vcn jpeg ring typeBoyuan Zhang2018-10-231-0/+1
| | | | | | | Add a new ring type for vcn jpeg. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add vcn jpeg decode interfaceBoyuan Zhang2018-10-231-0/+90
| | | | | | | Add VCN Jpeg decode interfaces and register defines. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: move radeon decoder define to header fileBoyuan Zhang2018-10-232-31/+32
| | | | | | | | Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h", so that it can be included by other files later. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* meson: update required amdgpu version to 2.4.95Boyuan Zhang2018-10-231-1/+1
| | | | | | | VCN jpeg requires new hw ip Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* configure.ac: update libdrm amdgpu version to 2.4.95Boyuan Zhang2018-10-231-1/+1
| | | | | | | VCN jpeg requires new hw ip Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radv: fix btoi for R32G32B32 when the dest offset is not 0Samuel Pitoiset2018-10-231-2/+2
| | | | | | Fixes: 593996bc02 ("radv: implement buffer to image operations for R32G32B32") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965/miptree: Use cpu tiling/detiling when mappingScott D Phillips2018-10-231-4/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the (un)map_gtt functions to (un)map_map (map by returning a map) and add new functions (un)map_tiled_memcpy that return a shadow buffer populated with the intel_tiled_memcpy functions. Tiling/detiling with the cpu will be the only way to handle Yf/Ys tiling, when support is added for those formats. v2: Compute extents properly in the x|y-rounded-down case (Chris Wilson) v3: Add units to parameter names of tile_extents (Nanley Chery) Use _mesa_align_malloc for the shadow copy (Nanley) Continue using gtt maps on gen4 (Nanley) v4: Use streaming_load_memcpy when detiling v5: (edited by Ken) Move map_tiled_memcpy above map_movntdqa, so it takes precedence. Add intel_miptree_access_raw, needed after rebasing on commit b499b85b0f2cc0c82b7c9af91502c2814fdc8e67. v6: refactor to changes done for sse41 separation (Tapani) Reviewed-by: Chris Wilson <[email protected]> (v5) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Tapani Pälli <[email protected]>
* i965/tiled_memcpy: inline movntdqa loads in tiled_to_linearScott D Phillips2018-10-239-90/+426
| | | | | | | | | | | | | | | | | | | | | | | | | The reference for MOVNTDQA says: For WC memory type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an aligned cache line without filling this data to the cache. [...] Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the temporary internal buffer if data is available. This hidden cache line sized temporary buffer can improve the read performance from wc maps. v2: Add mfence at start of tiled_to_linear for streaming loads (Chris) v3: add Android build support (Tapani) v4: squash 'fix i915: Fix streaming loads for intel_tiled_memcpy' separate sse41 to own static library (Tapani) Reviewed-by: Chris Wilson <[email protected]> (v2) Reviewed-by: Matt Turner <[email protected]> (v2) Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Tapani Pälli <[email protected]>
* i965: expose type of memcpy instead of memcpy function itselfTapani Pälli2018-10-234-30/+63
| | | | | | | | | | | There is currently no use of returned memcpy functions outside intel_tiled_memcpy. Patch changes intel_get_memcpy to return memcpy type instead of actual function. This makes it easier later to separate streaming load copy in to own static library. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* util: use *unsigned* ints for bit operationsEric Engestrom2018-10-231-1/+1
| | | | | | | | Fixes errors thrown by GCC's Undefined Behaviour sanitizer (ubsan) every time this macro is used. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radv: s/abs/fabsf/ for floatsEric Engestrom2018-10-231-4/+4
| | | | | | Fixes: a4c4efad89eceb26cf82 "radv: Rework guard band calculation" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: drop option description relicEric Engestrom2018-10-231-1/+1
| | | | | | | | | `platforms` is no longer a comma-separated string, and some of our option descriptions are way too long already. Just drop the incorrect bit. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* st/mesa: Record shader access qualifiers for imagesJason Ekstrand2018-10-235-9/+30
| | | | | | | | | | | | They're not required to be the same as the access flag on the image unit. For hardware that does shader image lowering based on the qualifier (Intel), it may be required for state setup. v2: (by Kenneth Graunke, incorporating feedback from Marek Olšák) - Reduce both access and shader_access to uint16_t to avoid making the pipe_image_view structure larger. Reviewed-by: Marek Olšák <[email protected]>
* nir/algebraic: Provide descriptive asserts for bit size checksJason Ekstrand2018-10-221-9/+42
| | | | | | | This will hopefully make debugging opt_algebraic bit-size compile failures easier. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/algebraic: Loosen a restriction on variablesJason Ekstrand2018-10-221-2/+6
| | | | | | | | | Previously, we would fail if a variable had an assigned but unknown bit size X and we tried to assign it an actual bit size. However, this is ok because, at the time we do the search, the variable does have an actual bit size and it will match X because of the NIR rules. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/algebraic: A bit of validation refactoring'Jason Ekstrand2018-10-221-15/+15
| | | | | | | We rename some local variables in validate() to be more readable and plumb the var through to get/set_var_bit_class instead of the var index. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/algebraic: Make internal classes str-ableJason Ekstrand2018-10-221-4/+12
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/algebraic: Generalize an optimizationJason Ekstrand2018-10-221-1/+1
| | | | | | There's nothing boolean about (a | ~a) ~> -1 Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/algebraic: Use bool internally instead of bool32Jason Ekstrand2018-10-222-8/+5
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Fix decoding for partial STATE_BASE_ADDRESS updates.Kenneth Graunke2018-10-222-6/+42
| | | | | | | | | | | STATE_BASE_ADDRESS only modifies various bases if the "modify" bit is set. Otherwise, we want to keep the existing base address. Iris uses this for updating Surface State Base Address while leaving the others as-is. v2: Also update aubinator_viewer_decoder (caught by Lionel) Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: Use nir_src_is_const and nir_src_as_* in core codeJason Ekstrand2018-10-2217-76/+56
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/search_helpers: Use nir_src_is_const and friendsJason Ekstrand2018-10-221-27/+22
| | | | | | | This not only makes them safe for more bit sizes but it also fixes a bug in is_zero_to_one where it would return true for constant NaN. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/search: Use nir_src_is_const and friendsJason Ekstrand2018-10-221-57/+13
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Add some new helpers for working with const sourcesJason Ekstrand2018-10-222-0/+108
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* mesa/st: Only call nir_lower_io_to_scalar_early on scalar ISAsAlyssa Rosenzweig2018-10-221-1/+4
| | | | | | | | | | | | | | | | | | | | | On scalar ISAs, nir_lower_io_to_scalar_early enables significant optimizations. However, on vector ISAs, it is counterproductive and impedes optimal codegen. This patch only calls nir_lower_io_to_scalar_early for scalar ISAs. It appears that at present there are no upstreamed drivers using Gallium, NIR, and a vector ISA, so for existing code, this should be a no-op. However, this patch is necessary for the upcoming Panfrost (Midgard) and Lima (Utgard) compilers, which are vector. With this patch, Panfrost is able to consume NIR directly, rather than TGSI with the TGSI->NIR conversion. For how this affects Lima, see https://www.mail-archive.com/[email protected]/msg189216.html Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* meson: don't require libelf for r600 without LLVMDylan Baker2018-10-221-8/+10
| | | | | | | | | | | r600 doesn't have a hard requirement on LLVM, and therefore doesn't have a hard requirement on libelf. Currently the logic doesn't allow that however. Distro-bug: https://bugs.gentoo.org/669058 Fixes: 5060c51b6f4dfb0d5358bde6523285163d3faaad ("meson: build r600 driver") Reviewed-by: Matt Turner <[email protected]>
* anv,radv: Trivially expose two new VK_GOOGLE extensionsJason Ekstrand2018-10-222-0/+4
| | | | | | | | | | | | This patch exposes support for the following two extensions: * VK_GOOGLE_decorate_string * VK_GOOGLE_hlsl_functionality1 There's nothing for the driver to do; it's all handled in spirv_to_nir. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107971 Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add no-op support for VK_GOOGLE_hlsl_functionality1Jason Ekstrand2018-10-222-0/+12
| | | | | | | | | | | This extension adds two new decorations which carry meaning only for HLSL shaders. They are expected to be handled by higher level layers and can be ignored by implementations. However, it does save the client a bit of work if the implementation safely ignores them instead of the client having to strip them out of the SPIR-V in order for it to be valid. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add support for SPV_GOOGLE_decorate_stringJason Ekstrand2018-10-221-0/+8
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* android: Build kms_swrast for the Android platformRob Herring2018-10-225-3/+38
| | | | | | Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* ac: Fix loading a dvec3 from an SSBOConnor Abbott2018-10-221-2/+2
| | | | | | | | | The comment was wrong, since the loop above casts to a type with the correct bitsize already. Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: Introduce ac_build_expand()Connor Abbott2018-10-222-14/+29
| | | | | | | | And implement ac_bulid_expand_to_vec4() on top of it. Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ir3/nir: Set up image_dims consts for image_deref_size intrinsic tooEduardo Lima Mitev2018-10-211-0/+1
| | | | | | | | | `nir_intrinsic_image_deref_size` is not being considered during scan for driver constants, so image constants are not emitted if a shader only ever query the size of an image (no load, store, atomic op, etc). This is unlikely, but possible. Reviewed-by: Rob Clark <[email protected]>
* nv50/ir: fix ConstantFolding::createMul for 64 bit mulsKarol Herbst2018-10-201-1/+1
| | | | | | | | Fixes: 2f52925f5c60c72c9389bfdc122c3d5f8e15b25f "nv50/ir: move a * b -> a << log2(b) code into createMul()" Reviewed-by: Rhys Perry <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
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