summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* nvc0: add conservative rasterization supportRhys Perry2018-04-307-8/+87
| | | | | | | | | Subpixel precision bias, dilation and the post-snap mode are supported on GM200 and newer. The pre-snap mode is supported for triangle primitives on GP100. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-303-0/+51
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add initial support for conservative rasterizationRhys Perry2018-04-3021-2/+243
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-3017-11/+526
| | | | | | | | Although the specs are written against compatibility GL 4.3 and allows core profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statementsBrian Paul2018-04-301-0/+6
| | | | | | | | | To silence warnings about unhandled switch values. Untested otherwise. v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric. Reviewed-by: Eric Anholt <[email protected]>
* tgsi: use enums instead of unsigned in ureg codeBrian Paul2018-04-302-12/+12
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* nir: move GL specific passes to src/compiler/glslTimothy Arceri2018-05-0112-38/+83
| | | | | | | With this we should have no passes in src/compiler/nir with any dependencies on headers from core GL Mesa. Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv/winsys: fix leaking resources from bo's imported by fdAndres Rodriguez2018-04-301-0/+1
| | | | | | | | | | | | A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.0 18.1 <[email protected]>
* i965/tiled_memcpy: ytiled_to_linear a cache line at a timeScott D Phillips2018-04-301-6/+66
| | | | | | | | | | | | Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain near WB readback performance when accessing the uncached ytiled memory, an order of magnitude improvement. Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Record mipmap resolver for unmappingChris Wilson2018-04-302-17/+22
| | | | | | | | | | | | When mapping a region of the mipmap_tree, record which complementary method to use to unmap it afterwards. By doing so we can avoid duplicating the decision tree used when mapping and thereby eliminate trivial errors that can be introduced if the two if-chains become out of sync. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_depthstencil before map_depthstencilChris Wilson2018-04-301-57/+57
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_etc before map_etcChris Wilson2018-04-301-21/+21
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_s8 before map_s8Chris Wilson2018-04-301-30/+30
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_movntdqa before map_movntdqaChris Wilson2018-04-301-12/+12
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_blit before map_blitChris Wilson2018-04-301-22/+22
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_gtt before map_gttChris Wilson2018-04-301-6/+6
| | | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* ac/nir: expand 64-bit vec3 loads to fix shuffling.Dave Airlie2018-05-011-0/+5
| | | | | | | | | | | | If loading 64-bit vec3 values, a 4 component load would be followed by a 2 component load and the resulting shuffle would fail as it requires 2 4 components. This just expands the second results vector out to 4 components. This fixes 100 CTS tests: dEQP-VK.spirv_assembly.type.vec3.*64* Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Don't stomp initial kflags for program cache.Kenneth Graunke2018-04-301-2/+2
| | | | | | | | | We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any existing kflags. Today, there are none (as the program cache doesn't support 48-bit addressing), but once we start using softpin, we'll need to preserve EXEC_OBJECT_PINNED. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Let batchbuffers be placed anywhere in the 48-bit address space.Kenneth Graunke2018-04-301-1/+1
| | | | | | | | | We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process. There's no reason to restrict batch buffers to the lower 4GB. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix check for 48b ppgtt supportScott D Phillips2018-04-305-61/+34
| | | | | | | | | | | | | | | | | The previous logic of the supports_48b_addresses wasn't actually checking if i915.ko was running with full_48bit_ppgtt. The ENOENT it was checking for was actually coming from the invalid context id provided in the test execbuffer. There is no path in the kernel driver where the presence of EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error. Instead, check the default context's GTT_SIZE param for a value greater than 4 GiB v2 (Ken): Fix in i965 as well. v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson) Reviewed-by: Kenneth Graunke <[email protected]>
* st/omx/enc: fix blit setup for YUV LoadImageLeo Liu2018-04-301-4/+4
| | | | | | | | | | | The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* autotools, meson: bump up required VA versionJuan A. Suarez Romero2018-04-302-2/+2
| | | | | | | | Due using a new VP9 config we use, required VA API 0.39 Fixes: 413c5ca3727 ("travis: update libva required version") CC: 18.1 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* docs: update calendar, add news and link release notes to 18.0.2Juan A. Suarez Romero2018-04-283-7/+8
| | | | Signed-off-by: Juan A. Suarez Romero <[email protected]>
* docs: add sha256 checksums for 18.0.2Juan A. Suarez Romero2018-04-281-1/+2
| | | | | Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit b3eed3ad03fd1eb61474cd0a8a173ad40fb8a876)
* docs: add release notes for 18.0.2Juan A. Suarez Romero2018-04-281-0/+143
| | | | | Signed-off-by: Juan A. Suarez Romero <[email protected]> (cherry picked from commit d38da7bd2d4387635fac8bc7f45e64f50dc43c43)
* radeonsi: increase the number of compiler threads depending on the CPUMarek Olšák2018-04-272-16/+29
| | | | | | | | | The compiler queue was limited to 3 threads, so shader-db running on a 16-thread CPU would have a bottleneck on the 3-thread queue. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: avoid a crash in gallivm_dispose_target_library_infoMarek Olšák2018-04-271-0/+3
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move data_layout into si_compilerMarek Olšák2018-04-273-6/+11
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move passmgr into si_compilerMarek Olšák2018-04-274-40/+32
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move target_library_info into si_compilerMarek Olšák2018-04-273-5/+13
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use si_compiler::triple in si_llvm_optimize_moduleMarek Olšák2018-04-271-2/+2
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add triple into si_compilerMarek Olšák2018-04-276-5/+13
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add struct si_compiler containing LLVMTargetMachineRefMarek Olšák2018-04-278-91/+101
| | | | | | | | It will contain more variables. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename r600_texture::resource to bufferMarek Olšák2018-04-2710-201/+201
| | | | | | r600_resource could be renamed to si_buffer. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use r600_resource() typecast helperMarek Olšák2018-04-2719-78/+80
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove unused atom parameter from si_atom::emitMarek Olšák2018-04-2710-36/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: inline 2 trivial state structuresMarek Olšák2018-04-275-19/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove function si_init_atomMarek Olšák2018-04-274-27/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove si_atom::idMarek Olšák2018-04-274-28/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use an indirect table for state atomsMarek Olšák2018-04-2714-172/+148
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename r600_atom -> si_atomMarek Olšák2018-04-2710-76/+76
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_pipe_common.hMarek Olšák2018-04-2714-347/+302
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: workaround for INTERP with indirect indexingMarek Olšák2018-04-271-6/+13
| | | | | | | and clean up the conditions. Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 18.0 18.1 <[email protected]>
* radeonsi: rewrite DCC format compatibility checking codeMarek Olšák2018-04-271-56/+42
| | | | | | It might be better to use a slow compressed clear when clearing to 1. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement DCC fast clear swizzle constraints more accuratelyMarek Olšák2018-04-273-35/+65
| | | | | | | | | | Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear value of 1. This significantly changes the DCC fast clear code, and fixes fast clear for RGB formats without alpha. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename variables and document stuff around DCC fast clearMarek Olšák2018-04-271-41/+42
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fully enable 2x DCC MSAA for array and non-array texturesMarek Olšák2018-04-274-14/+20
| | | | | | | The clear code is exactly the same as for 1 sample buffers - just clear the whole thing. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VIMarek Olšák2018-04-272-9/+24
| | | | | | | GFX9 is more complicated and needs a compute shader that we should just copy from amdvlk. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: handle DCC subresource fast clear restriction on VIMarek Olšák2018-04-271-1/+20
| | | | | | | v2: require the previous level to be clearable for determining whether the last unaligned level is clearable Reviewed-by: Nicolai Hähnle <[email protected]>
* swr/rast: No need to export GetSimdValidIndicesGfxGeorge Kyriazis2018-04-271-4/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 19:11:36 +0000