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* radeon/video: enable HEVC main 10 decodeBoyuan Zhang2016-03-111-2/+6
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965/chv: Display proper brandingBen Widawsky2016-03-114-7/+33
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Update lower min for CS threadsBen Widawsky2016-03-111-1/+1
| | | | | | | | We have better information now, and 28 was not a valid thing to support. 6 EUs per sublice with 7 threads per EU is the minimum supported config. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Check that compute threads are above thresholdBen Widawsky2016-03-112-0/+9
| | | | | | | | | | | | | The way we are organizing this code, the statically configured max_cs_threads should always be the minimum value we actually support (ie. are aware of). As a result, we can fall back to that if we get invalid numbers from the kernel (ie. when the query succeeds, but the result is lower than expected). I was originally planning to use an assert, but there is no reason to be so mean. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965/chv: Use kernel provided info for max_cs_threadsBen Widawsky2016-03-111-1/+8
| | | | | | | | | | | | | With the previous patches, the code can find out the actual number of available compute threads. It is enabled only for Cherryview since that is the only platform I know for a fact has shipped devices which can benefit from this. It seems like other platforms /might/ benefit from this because of fused configurations which /might/ have shipped. Fallback code is still there. v2: Some minor adjustments from Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965: Query and store GPU properties from kernelBen Widawsky2016-03-112-1/+31
| | | | | | | | | | | | | | | | | Certain products are not uniquely identifiable based on device id alone. The kernel exports an interface to help deal with this. This patch merely introduces the consumer of the interface and makes sure nothing breaks. It is also possible to use these values for programming GPGPU mode, and I plan to do that as well. The interface was introduced in libdrm 2.4.60, which is already required, so it should all be fine. v2: Some minor changes recommended by Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* st/mesa: check that the image unit is valid in st_bind_imagesNicolai Hähnle2016-03-111-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-112-5/+8
| | | | | | | | | | Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. v3: Check that we have a real texture (Nicolai) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove ST_NEW_MESA flag (v2)Marek Olšák2016-03-114-6/+4
| | | | | | | | Only used indirectly when checking dirty.st != 0 v2: also update st_cb_compute.c Reviewed-by: Ilia Mirkin <[email protected]>
* r600g: clear compressed_depthtex/colortex_mask when binding buffer textureNicolai Hähnle2016-03-111-12/+12
| | | | | | | | | | | Found by inspection of the source based on a bisected bug report. This bug has been in the code for a long time, but the more recent PBO upload feature exposed it because it leads to more uses of buffer textures. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94388 Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0 11.1 11.2" <[email protected]>
* st/mesa: add GL_ARB_shader_atomic_counter_ops supportIlia Mirkin2016-03-103-7/+58
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add GL_ARB_shader_atomic_counter_ops supportIlia Mirkin2016-03-106-0/+118
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: add support for TGSI FMA opsIlia Mirkin2016-03-102-1/+7
| | | | | | | | This will allow the nouveau backend to not try and split up ops that are fused in GLSL. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-103-2/+51
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move si_decompress_textures to si_blit.cNicolai Hähnle2016-03-103-23/+23
| | | | | | | | | Since it is all about calling into blitter functions, it makes more sense here. This change also reduces the size of the interfaces between .c files. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-101-0/+30
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: notify all contexts when cmasks are enabled/disabledNicolai Hähnle2016-03-102-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an annoying corner case that I stumbled across while looking into piglit's arb_shader_image_load_store/execution/load-from-cleared-image.shader_test (which can be easily adapted to demonstrate the bug without the ARB_shader_image_load_store extension) When we bind a texture and then clear it using glClear (by attaching it to the current framebuffer) for the first time, we allocate a separate cmask for the texture to do fast clear, but the corresponding bit in compressed_colortex_mask is not set. Subsequent rendering will use incorrect data. Conversely, when a currently bound texture with an existing cmask is exported leading to that cmask being disabled, the compressed_colortex_mask bit will remain set, leading to an assertion later on in debug builds. Since iterating through all contexts and/or remembering where every texture is bound would be costly, and cmask enable/disable should be rare, we will maintain a global counter to signal contexts that they must update their compressed_colortex_masks. This patch introduces the global counter, and subsequent patches will do the mask update. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Set a proper _BaseFormat for window system renderbuffers in ES.Kenneth Graunke2016-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | intel_alloc_private_renderbuffer_storage did: rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat); Unfortunately, internalFormat was usually an unsized format (such as GL_DEPTH_COMPONENT). In OpenGL ES, _mesa_base_fbo_format() refuses to accept unsized formats, and returns 0 rather than a real base format. This meant that we ended up with a completely bogus rb->_BaseFormat for window system buffers on OpenGL ES. All other renderbuffer allocation functions in intel_fbo.c instead use the mesa_format, and do: rb->_BaseFormat = _mesa_get_format_base_format(...); We can do likewise, using rb->Format. This appears to work just fine. dEQP-GLES3.functional.state_query.fbo.framebuffer_attachment_x_size_initial failed, as it tried to perform a GL_FRAMEBUFFER_ATTACHMENT_DEPTH_SIZE query on the window system depth buffer. That query relies on a proper rb->_BaseFormat being set, so it broke because rb->_BaseFormat was 0 due to the above bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94458 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* glcpp: Fix locations when encounting "#<NEWLINE>".Kenneth Graunke2016-03-102-1/+4
| | | | | | | | | | | | | | | We were failing to reset our location tracking when encountering a NEWLINE in the <HASH> state. Rip the code from the <*>{NEWLINE} rule, which handles this properly. Also, update 146-version-first-hash.c to have proper expectations. When I introduced the test, I didn't verify that the line/column numbers were correct, and it turns out they varied based on the type of newline ending. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94447 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* gallium/swr: remove use of BYTE from swr driverTim Rowley2016-03-104-14/+14
| | | | | | Remove use of a win32-style type leaked from the swr rasterizer. Reviewed-by: Bruce Cherniak <[email protected]>
* nvc0: expose SM35 perf counters to AMD_performance_monitorSamuel Pitoiset2016-03-101-2/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add driver metrics for SM35 (GK110)Samuel Pitoiset2016-03-101-1/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add MP performance counters for SM35 (GK110)Samuel Pitoiset2016-03-103-17/+204
| | | | | | | | | Because compute support is not enabled by default for these chipsets, NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable performance counters. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: explode config of Kepler hardware SM eventsSamuel Pitoiset2016-03-101-78/+477
| | | | | | | | This is really verbose but most of the configuration will be reused for SM35 (GK110). Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: rework the driver metrics infrastructureSamuel Pitoiset2016-03-103-157/+172
| | | | | | | This follows the same design as MP perf counters. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: rework the MP counters infrastructureSamuel Pitoiset2016-03-104-268/+243
| | | | | | | This mainly improves how we define the different list of queries. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* egl: clean up typedef madness in the backend APIMarek Olšák2016-03-102-155/+155
| | | | | | let's use the dd.h format Reviewed-by: Emil Velikov <[email protected]>
* glsl: report correct number of allowed vertex inputs and fragment outputsIago Toral Quiroga2016-03-101-3/+4
| | | | | | | | | | | | Before we would always report 16 for both and we would only fail if either one exceeded 16. Now we fail if the maximum for each is exceeded, even if it is smaller than 16 and we report the correct maximum. Also, expand the size of to_assign[] to 32. There is code at the top of the function handling max_index up to 32, so this just makes the code more consistent. Reviewed-by: Timothy Arceri <[email protected]>
* nouveau: Fix clang reserved-user-defined-literal error.Vinson Lee2016-03-091-1/+1
| | | | | | | | | | | | CXX codegen/nv50_ir.lo In file included from codegen/nv50_ir.cpp:28: ./nouveau_debug.h:19:30: error: invalid suffix on literal; C++11 requires a space between literal and identifier [-Wreserved-user-defined-literal] fprintf(stderr, "%s:%d - "fmt, __FUNCTION__, __LINE__, ##args) ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: Make glGetInteger64v convert float/doubles to 32-bit integers.Kenneth Graunke2016-03-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the GL 4.4 core specification, section 2.2.2 ("Data Conversions For State Query Commands"): "If a command returning integer data is called, such as GetIntegerv or GetInteger64v, a boolean value of TRUE or FALSE is interpreted as one or zero, respectively. A floating-point value is rounded to the nearest integer, unless the value is an RGBA color component, a DepthRange value, or a depth buffer clear value. In these cases, the query command converts the floating-point value to an integer according to the INT entry of table 18.2; a value not in [−1, 1] converts to an undefined value." The INT entry of table 18.2 shows that b = 32, meaning the expectation is to convert it to a 32-bit integer value. Fixes: dEQP-GLES3.functional.state_query.floats.blend_color_getinteger64 dEQP-GLES3.functional.state_query.floats.color_clear_value_getinteger64 dEQP-GLES3.functional.state_query.floats.depth_clear_value_getinteger64 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94456 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* gallium/radeon: use explicit drm_major, drm_minor checkEmil Velikov2016-03-091-1/+2
| | | | | | | | | | Just like everywhere else in the radeon codebase. v2: Don't forget about drm_major == 3 (Alex) Cc: Alex Deucher <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/x11: check the return value of xcb_dri2_get_buffers_reply()Emil Velikov2016-03-091-0/+3
| | | | | | | | | | | ... before using it. The function can return NULL, which we should check prior to refererencing it in the next function(s). Cc: Fabian Vogt <[email protected]> Cc: "11.1 11.2" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93667 Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* gallium: do not wrap header inclusion inEmil Velikov2016-03-099-19/+28
| | | | | | | | | | | | | | | | Add one missing extern C guard within include/pipe/p_video_enums.h, and remove the wrapping throughout gallium. On Haiku one could even use the gallium debug_printf() although that's another topic. v2: Leave dbghelp.h as is (Jose) Cc: Jose Fonseca <[email protected]> Cc: Brian Paul <[email protected]> Cc: Alexander von Gluck IV <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* opencl: fix .gitignore for .install-gallium-linksDieter Nützel2016-03-091-0/+1
| | | | | | | | | | | Fixes: 0b6157e9713 "install-gallium-links: port changes from install-lib-links" v2: move this to the top level .gitignore and added Fixes: like Emil Velikov <[email protected]> suggested Signed-off-by: Dieter Nützel <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl: remove remnants of MESA_drm_displayEmil Velikov2016-03-093-21/+0
| | | | | | | Last set in st/egl, unused in mesa-demos and superseded by EGL_KHR_platform_gbm. Signed-off-by: Emil Velikov <[email protected]>
* egl: remove final pieces of KHR_vg_parent_imageEmil Velikov2016-03-092-2/+0
| | | | | | Similar to previous commit - unused/unset for a long time. Signed-off-by: Emil Velikov <[email protected]>
* glapi: remove the final function offset tagsEmil Velikov2016-03-094-30/+30
| | | | | | | | | | | | A commit earlier this year reworked out python scripts to use a separate file for these. Followed by removing support from the parser, and removing all of the offset tags. Seems like we either missed a few, or people added them by mistake. Either way let's nuke the ones that are still around. Cc: Ian Romanick <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* winsys/amdgpu/addrlib: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* i915: limit extern "C" hack only for libdrm headersEmil Velikov2016-03-091-7/+6
| | | | Signed-off-by: Emil Velikov <[email protected]>
* xmesa: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+4
| | | | Signed-off-by: Emil Velikov <[email protected]>
* util/sha: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | Signed-off-by: Emil Velikov <[email protected]>
* egl/wayland: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-4/+4
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gbm: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-5/+5
| | | | Signed-off-by: Emil Velikov <[email protected]>
* st/mesa: shader image atoms must be before framebuffer updateNicolai Hähnle2016-03-091-6/+6
| | | | | | | | | | | | | The reason is that the shader image atoms call st_finalize_texture, which may set ST_NEW_FRAMEBUFFER. This fixes an assertion triggered by a subtest of piglit's arb_shader_image_load_store-invalid. v2: add comment explaining order constraints (suggested by Ilia) Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallivm: special case TGSI_OPCODE_STORENicolai Hähnle2016-03-091-1/+1
| | | | | | | | This instruction has the resource (buffer or image) as a destination to represent the writemask for SSBO writes. However, this is obviously not a "real" destination for the purpose of emitting LLVM IR. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: set correct output mode for RESQNicolai Hähnle2016-03-091-1/+1
| | | | | Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add CAPs returning PCI device locationMarek Olšák2016-03-0916-0/+76
| | | | Reviewed-by: Brian Paul <[email protected]>
* winsys/amdgpu: get PCI infoMarek Olšák2016-03-092-2/+21
| | | | | | | | | This will be queried by the OpenCL stack using an interop call. I have tested that the values match lspci. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
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