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* intel/isl: Add surface state clear value informationNanley Chery2017-07-222-0/+13
* anv: Transition MCS buffers from the undefined layoutNanley Chery2017-07-223-18/+35
* intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand2017-07-221-7/+23
* i965/bufmgr: Add comments about GTT coherency issues.Chris Wilson2017-07-221-0/+22
* i965: Drop non-LLC lunacy in the program cache code.Kenneth Graunke2017-07-223-70/+21
* i965: Set MAP_PERSISTENT on program cache buffers.Kenneth Graunke2017-07-221-4/+8
* i965: Correctly set MAP_WRITE when creating the LLC program cache map.Kenneth Graunke2017-07-221-1/+1
* i965/bufmgr: Use write-combine mappings where availableMatt Turner2017-07-221-3/+88
* i965/bufmgr: Skip wait ioctl when not busy.Kenneth Graunke2017-07-221-0/+4
* i965/bufmgr: Explicitly wait instead of using I915_GEM_SET_DOMAIN.Kenneth Graunke2017-07-221-17/+6
* i965/bufmgr: Allocate BO pages outside of the kernel's locking.Kenneth Graunke2017-07-221-0/+13
* glsl: rework misleading block layout codeTimothy Arceri2017-07-231-4/+4
* glsl: remove placeholder commentTimothy Arceri2017-07-231-4/+0
* st/mesa: use proper resource target type in st_AllocTextureStorage()Brian Paul2017-07-221-1/+4
* mesa: remove pointless assignments in init_teximage_fields_ms()Brian Paul2017-07-221-3/+0
* svga: Limit number of immediates in shaderNeha Bhende2017-07-221-3/+5
* svga: fix constant indices for texcoord scale factors and texture buffer sizeCharmaine Lee2017-07-221-9/+6
* svga: fix unnormalized->normalized texture coordinate conversionNeha Bhende2017-07-223-3/+35
* svga: only support 4x, 8x, 16x msaaBrian Paul2017-07-221-0/+5
* mesa: include texture size in error messagesBrian Paul2017-07-221-4/+5
* i965: Support the mesa_no_error driconf option.Kenneth Graunke2017-07-222-0/+4
* anv/blorp: Assert isl_surf_init success in do_buffer_copyJason Ekstrand2017-07-221-13/+15
* anv/blorp: Explicitly set row_pitch in do_buffer_copyJason Ekstrand2017-07-221-1/+1
* i965: Delete gen8_draw_upload.cKenneth Graunke2017-07-221-0/+0
* nv50/ir: disable mul+add to mad for precise instructionsKarol Herbst2017-07-211-2/+3
* nv50/ir/tgsi: handle precise for most ALU instructionsKarol Herbst2017-07-211-0/+2
* nv50/ir: add precise field to InstructionKarol Herbst2017-07-212-0/+3
* st/glsl_to_tgsi: don't optimize mul+add to mad if expression is preciseKarol Herbst2017-07-211-1/+1
* gallium/docs: add precise instruction modifierKarol Herbst2017-07-211-1/+10
* tgsi/text: parse _PRECISE modifierKarol Herbst2017-07-211-3/+14
* tgsi: populate preciseKarol Herbst2017-07-218-30/+51
* st/glsl_to_tgsi: handle precise modifierKarol Herbst2017-07-211-0/+13
* tgsi/dump: print _PRECISE modifier on InstructionsKarol Herbst2017-07-211-0/+4
* tgsi: add precise flag to tgsi_instructionKarol Herbst2017-07-212-1/+3
* i965: Set lower_vote_trivial in vector_nir_options_gen6 too.Kenneth Graunke2017-07-211-0/+1
* radv: reset non-syncobj semaphore context after wait.Dave Airlie2017-07-221-0/+2
* st/mesa: add destroy_drawable interfaceCharmaine Lee2017-07-207-3/+123
* radv: rebase radv_entrypoints_gen.py on anv_entrypoints_gen.pyDylan Baker2017-07-212-275/+287
* i965/miptree: Clean-up unusedTopi Pohjolainen2017-07-2214-1646/+96
* i965/miptree: Switch remaining surfaces to islTopi Pohjolainen2017-07-222-93/+41
* i965/miptree: Drop miptree_array_layout in get_isl_dim_layout()Topi Pohjolainen2017-07-223-11/+8
* i965/miptree: Relax size alignment for linear surfacesTopi Pohjolainen2017-07-221-1/+6
* i965/miptree: Store compression flag also for isl basedTopi Pohjolainen2017-07-221-0/+1
* i965/miptree: Check tex image allocation failuresTopi Pohjolainen2017-07-221-0/+2
* main/teximage: Even on failure use valid format for init()Topi Pohjolainen2017-07-221-1/+1
* intel/isl/gen7: Don't allow multisampled surfaces with valign2Topi Pohjolainen2017-07-221-19/+23
* intel/isl/gen7: Allow msaa with signed integer formatsTopi Pohjolainen2017-07-221-2/+3
* intel/isl/gen7: Allow msaa with 128-bit formatsTopi Pohjolainen2017-07-221-4/+7
* intel/isl: Allow 1D surfaces with compressed formatsTopi Pohjolainen2017-07-221-1/+1
* intel/isl: Align non-tiled horizontally by cache lineTopi Pohjolainen2017-07-221-1/+15
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