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* freedreno/ir3: ignore clip-vertex varyingRob Clark2016-01-301-1/+4
| | | | | | | | | | | Since we emulate clip-planes, the clip-vertex is used within the VS itself (thanks to nir_lower_clip). So just ignore it as a VS output. Fixes a boatload of piglit tests that were asserting on unknown varying slot. (Also unrelated spelling/typo fix.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't ignore local varsRob Clark2016-01-301-1/+7
| | | | | | | | | | | With glsl_to_nir we end up with local variables, instead of global, for arrays. Note that we'll eventually have to do something more clever, I think, when we support multiple functions, but that will probably take some work in a few places. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle tex instrs w/ const offsetRob Clark2016-01-301-0/+16
| | | | | | Something we start to see with glsl_to_nir. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: support load_front_face intrinsicRob Clark2016-01-301-2/+14
| | | | | | | With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE. But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: limit string marker to max packet sizeRob Clark2016-01-301-0/+3
| | | | | | Experimentally derived max size. Signed-off-by: Rob Clark <[email protected]>
* nvc0: avoid crashing when there are holes in vertex array bindingsIlia Mirkin2016-01-291-3/+13
| | | | | | | | | When using the "shared" vertex array configuration strategy, we bind each of the buffers as a separate array. However there can be holes in such vertex buffer lists, so just emit a disable for those. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: enable atomic counters and ssboIlia Mirkin2016-01-294-4/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: handle new TGSI MEMBAR opcodeIlia Mirkin2016-01-291-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin2016-01-293-5/+8
| | | | | | | Teach the emitter that the two registers are sequential, and drop the second arg entirely, in favor of a double-wide first argument. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for indirect buffer loadingIlia Mirkin2016-01-292-10/+31
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add SUQ op by reading the info from driver constbufIlia Mirkin2016-01-296-3/+21
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-296-11/+147
| | | | | | | This largely leaves the existing image logic alone. When image support is added this will have to be harmonized somehow. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: handle shader buffer memory barrierIlia Mirkin2016-01-291-0/+4
| | | | | | | Issue a MEM_BARRIER. No idea if this is sufficient. As there are no tests for this, it'll have to do for now. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add state management for shader buffersIlia Mirkin2016-01-295-8/+111
| | | | | | | (address, length) pairs are uploaded to the driver constbuf as well to make these values available to the shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: double per-shader stage driver constants areaIlia Mirkin2016-01-293-15/+15
| | | | | | We need to store a lot more info now with per-buffer address/size. Signed-off-by: Ilia Mirkin <[email protected]>
* trace: add support for set_shader_buffersIlia Mirkin2016-01-293-0/+60
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add arg_begin/arg_end around buffer array Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: enable ARB_shader_storage_buffer_object when supportedIlia Mirkin2016-01-291-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add shader buffer barrier bitIlia Mirkin2016-01-292-0/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add support for memory barrier intrinsicsIlia Mirkin2016-01-291-0/+45
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2) v1 -> v2: use TGSI_MEMBAR defines
* st/mesa: use RESQ to find buffer sizeIlia Mirkin2016-01-291-4/+18
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: add support for SSBO binding and GLSL intrinsicsIlia Mirkin2016-01-299-8/+397
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> v1 -> v2: some 80 char reformatting
* st/mesa: add atomic counter supportIlia Mirkin2016-01-2910-8/+330
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add PROGRAM_IMMEDIATE, PROGRAM_BUFFERIlia Mirkin2016-01-292-1/+2
| | | | | | | | | This makes PROGRAM_IMMEDIATE a first-class gl_register_file type, and adds PROGRAM_BUFFER to the list. These are used purely inside glsl_to_tgsi conversion. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: keep track of ssbo variable being accessed, add access paramsIlia Mirkin2016-01-295-6/+57
| | | | | | | | | | | | | | | | | | | | Currently any access params (coherent/volatile/restrict) are being lost when lowering to the ssbo load/store intrinsics. Keep track of the variable being used, and bake its access params in as the last arg of the load/store intrinsics. If the variable is accessed via an instance block, then 'variable' points to the instance block variable and not the field inside the instance block that we are accessing. In order to check access parameters for the field itself we need to detect this case and keep track of the corresponding field struct so we can extract the specific field access information from there instead. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add tracking of struct field v2 -> v3: minor adjustments based on Iago's feedback Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl: always initialize image_* fields, copy them on interface initIlia Mirkin2016-01-293-1/+12
| | | | | | | | | Interfaces can have image properties set in case they are buffer interfaces. Make sure not to lose this information. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsicsIlia Mirkin2016-01-293-2/+24
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add defines for the various bits Reviewed-by: Roland Scheidegger <[email protected]>
* winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*Michel Dänzer2016-01-291-10/+9
| | | | | | | | | | | In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created in VRAM if they get evicted to GTT. In general there's no need to restrict any of the flags to any particular domains. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESSMichel Dänzer2016-01-291-0/+2
| | | | | | | | | | | | | | | | Failing to do this was resulting in the kernel driver unnecessarily leaving open the possibility of CPU access to tiled BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862 (This change shouldn't be backported to stable branches, because released versions of xf86-video-amdgpu unnecessarily try to map the front buffer) Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* nv50/ir: optimize mad/fma with third argument 0 to mulKarol Herbst2016-01-281-0/+21
| | | | | | | | | | | | | | | Very modest effect, but it's clearly the right thing to do. total instructions in shared programs : 6131491 -> 6131398 (-0.00%) total gprs used in shared programs : 910157 -> 910131 (-0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst bytes helped 0 55 85 85 hurt 0 26 20 20 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: run DCE backwardsKarol Herbst2016-01-281-3/+3
| | | | | | | Reduces calls up to 50% Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))Karol Herbst2016-01-281-0/+8
| | | | | | | | | | | | | | | Following shader-db results on GK110: total instructions in shared programs : 6141510 -> 6131491 (-0.16%) total gprs used in shared programs : 910187 -> 910157 (-0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst bytes helped 0 18 821 821 hurt 0 0 0 0 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: disallow implicit conversions in ESSL shadersIlia Mirkin2016-01-282-0/+11
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: Add option for SI schedulerAxel Davy2016-01-283-1/+7
| | | | | | | | | | Add a debug option to select the LLVM SI Machine Scheduler. R600_DEBUG=sisched Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: double-precision values don't support interpolationSamuel Iglesias Gonsálvez2016-01-281-2/+7
| | | | | | | | | | | | | | | | | | | | ARB_gpu_shader_fp64 spec says: "This extension does not support interpolation of double-precision values; doubles used as fragment shader inputs must be qualified as "flat"." Fixes the regressions added by commit 781d278: arb_gpu_shader_fp64-double-gettransformfeedbackvarying arb_gpu_shader_fp64-tf-interleaved arb_gpu_shader_fp64-tf-interleaved-aligned arb_gpu_shader_fp64-tf-separate Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93878 Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* vc4: Throttle outstanding rendering after submission.Eric Anholt2016-01-271-0/+9
| | | | | | | | | | | Just make sure that after we've submitted, we get to at least 5 (global) submits ago before we go on to do more. Prevents up to seconds of lag with window movement in X with xcompmgr -c. There may be useful tuning to do in the future, but for now this gets us usability. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* vc4: Don't record the seqno of a failed job submit.Eric Anholt2016-01-271-2/+2
| | | | | | | | | On an error return, the returned seqno will probably be unset, so we'd lose track of what we've submitted so far for waiting on in the future. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* i965/skl: Utilize new 5th bit for gateway messagesBen Widawsky2016-01-271-2/+4
| | | | | | | | Modify comment as spotted by Matt, and Chris Forbes Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl: only expose double mod when doubles are availableIlia Mirkin2016-01-271-17/+18
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nv50/ir: fix memory corruption when spilling and redoing RAKarol Herbst2016-01-261-0/+3
| | | | | | | | | | | When RA fails, and we spill, we have to clean everything up before doing RA again. We were forgetting to reset the hi/lo linked lists - at least the hi list is guaranteed to still have pointers to now-deleted RIG nodes. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* glsl: remove old FINISHMETimothy Arceri2016-01-271-2/+0
| | | | | | This should have been removed long ago. Reviewed-by: Chris Forbes <[email protected]>
* configure.ac: don't require EGL/DRM and GBM if OpenGL is disabledMarek Olšák2016-01-261-0/+5
| | | | | | | This allows building VDPAU/OMX/VA drivers without OpenGL and its dependencies. Reviewed-by: Michel Dänzer <[email protected]>
* r600,compute: Plug few memory leaksJan Vesely2016-01-268-21/+55
| | | | | | | | | | | v2: drop inline keyword drop radeon_llvm_dispose_kernel_module wrapper v3: move definitions to .c file use in radeonsi Signed-off-by: Jan Vesely <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600: Typos and whitespace fixesJan Vesely2016-01-263-7/+7
| | | | | | Signed-off-by: Jan Vesely <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix clover crashMarek Olšák2016-01-261-1/+1
| | | | | | caused by ce1e7784d08a14a90e6051915f2622424a54dc6e Trivial.
* radeonsi: fix shader precompilation for shader-dbMarek Olšák2016-01-261-9/+35
| | | | | | | | | | The addition of spi_shader_col_format killed all color outputs in precompiled shaders. Reviewed-by: Michel Dänzer <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1) v2: also set the alpha func (trivial)
* glsl: add GL_OES_geometry_point_size and conditionalize gl_PointSizeIlia Mirkin2016-01-265-1/+17
| | | | | | | | | | | For now this will be enabled in tandem with GL_OES_geometry_shader. Should a driver come along that wants to separate them out, another enable can be added. Also adds the missed GL_OES_geometry_shader define in glcpp. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* glsl: move to compiler/Emil Velikov2016-01-26497-84/+498
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* nir: move to compiler/Emil Velikov2016-01-26105-157/+310
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* compiler: move the glsl_types C wrapper alongside their C++ brethrenEmil Velikov2016-01-266-7/+8
| | | | | | | | | | At a later stage we might want to split out the NIR specific [XXX: which one was it], as to make things move obvious and rename the files appropriately. This patch aims to split it out of nir. Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* nir: move glsl_types.{cpp,h} to compilerEmil Velikov2016-01-2670-76/+68
| | | | | | | | Allows us to remove the SCons workaround :-) Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jose Fonseca <[email protected]>
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