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* xorg/vmwgfx: Make vmwarectrl work also on 64-bit serversThomas Hellstrom2010-10-121-0/+1
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* st/xorg: Don't try to use option values before processing optionsThomas Hellstrom2010-10-121-13/+13
| | | | Signed-off-by: Thomas Hellstrom <[email protected]>
* Revert "llvmpipe: try to keep plane c values small"Keith Whitwell2010-10-122-24/+17
| | | | | | | This reverts commit 9773722c2b09d5f0615a47cecf4347859474dc56. Looks like there are some floor/rounding issues here that need to be better understood.
* gallivm: don't branch on KILLs near end of shaderKeith Whitwell2010-10-121-10/+47
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* r600g: add missing file to sconscriptKeith Whitwell2010-10-121-0/+1
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* gallium: move sse intrinsics debug helpers to u_sse.hKeith Whitwell2010-10-123-117/+79
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* llvmpipe: Fix MSVC build.José Fonseca2010-10-121-18/+18
| | | | MSVC doesn't accept more than 3 __m128i arguments.
* llvmpipe: fix typo in last commitKeith Whitwell2010-10-121-2/+2
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* llvmpipe: try to keep plane c values smallKeith Whitwell2010-10-122-17/+24
| | | | Avoid accumulating more and more fixed point bits.
* llvmpipe: add debug helpers for epi32 etcKeith Whitwell2010-10-121-0/+115
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* llvmpipe: try to do more of rast_tri_3_16 with intrinsicsKeith Whitwell2010-10-122-9/+271
| | | | | | | | There was actually a large quantity of scalar code in these functions previously. This tries to move more into intrinsics. Introduce an sse2 mm_mullo_epi32 replacement to avoid sse4 dependency in the new rasterization code.
* llvmpipe: Do not dispose the execution engine.José Fonseca2010-10-121-3/+0
| | | | The engine is a global owned by gallivm module.
* nouveau: Get larger push buffers.Francisco Jerez2010-10-123-3/+3
| | | | | Useful to amortize the command submission/reloc overhead (e.g. etracer goes from 72 to 109 FPS on nv4b).
* dri/nouveau: Initialize tile_flags when allocating a render target.Francisco Jerez2010-10-122-6/+14
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* r600g: fix typo in vertex sampling on r600Dave Airlie2010-10-121-1/+1
| | | | | | fixes https://bugs.freedesktop.org/show_bug.cgi?id=30771 Reported-by: Kevin DeKorte
* i965: Always use the new FS backend on gen6.Eric Anholt2010-10-111-2/+7
| | | | | | | | | | It's now much more correct for gen6 than the old backend, with just 2 regressions I've found (one of which is common with pre-gen6 and will be fixed by an array splitting IR pass). This does leave the old Mesa IR backend getting used still when we don't have GLSL IR, but the plan is to get GLSL IR input to the driver for the ARB programs and fixed function by the next release.
* i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.Eric Anholt2010-10-111-6/+15
| | | | | | | | | | | | | Pre-gen6, you could mix int and float just fine. Now, you get goofy results. Fixes: glsl-arb-fragment-coord-conventions glsl-fs-fragcoord glsl-fs-if-greater glsl-fs-if-greater-equal glsl-fs-if-less glsl-fs-if-less-equal
* i965: Don't compute-to-MRF in gen6 VS math.Eric Anholt2010-10-111-7/+15
| | | | | There was code to do this for pre-gen6 already, this just enables it for gen6 as well.
* i965: Expand uniform args to gen6 math to full registers to get hstride == 1.Eric Anholt2010-10-111-0/+25
| | | | | | | | | | This is a hw requirement in math args. This also is inefficient, as we're calculating the same result 8 times, but then we've been doing that on pre-gen6 as well. If we're doing math on uniforms, though, we'd probably be better served by having some sort of mechanism for precalculating those results into another uniform value to use. Fixes 7 piglit math tests.
* i965: Don't compute-to-MRF in gen6 math instructions.Eric Anholt2010-10-111-0/+16
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* i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt2010-10-111-0/+26
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* i965: Don't consider gen6 math instructions to write to MRFs.Eric Anholt2010-10-111-17/+38
| | | | | This was leftover from the pre-gen6 cleanups. One tests regresses where compute-to-MRF now occurs.
* glsl: Changes in generated file glsl_lexer.cppChad Versace2010-10-111-691/+716
| | | | Signed-off-by: Ian Romanick <[email protected]>
* glsl: Add lexer rules for uint and uvecN (N=2..4)Chad Versace2010-10-111-0/+4
| | | | | | Commit for generated file glsl_lexer.cpp follows this commit. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add glsl_type::uvecN_type for N=2,3Chad Versace2010-10-112-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* intel_extensions: Add ability to set GLSL version via environmentChad Versace2010-10-111-1/+18
| | | | | | | | | Add ability to set the GLSL version used by the GLcontext by setting the environment variable INTEL_GLSL_VERSION. For example, env INTEL_GLSL_VERSION=130 prog args If the environment variable is missing, the GLSL versions defaults to 120. Reviewed-by: Ian Romanick <[email protected]>
* r200: revalidate after radeon_update_renderbuffersDaniel Vetter2010-10-113-3/+10
| | | | | | | | | | | | | | | | | By calling radeon_draw_buffers (which sets the necessary flags in radeon->NewGLState) and revalidating if NewGLState is non-zero in r200TclPrimitive. This fixes an assert in libdrm (the color-/ depthbuffer was changed but not yet validated) and and stops the kernel cs checker from complaining about them (when they're too small). Thanks to Mario Kleiner for the hint to call radeon_draw_buffer (instead of my half-broken hack). v2: Also fix the swtcl r200 path. Cc: Mario Kleiner <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
* i965: Compute to MRF in the new FS backend.Eric Anholt2010-10-112-0/+124
| | | | | | This didn't produce a statistically significant performance difference in my demo (n=4) or nexuiz (n=3), but it still seems like a good idea and is recommended by the HW team.
* i965: Give the FB write and texture opcodes the info on base MRF, like math.Eric Anholt2010-10-112-38/+48
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* i965: Give the math opcodes information on base mrf/mrf len.Eric Anholt2010-10-112-12/+57
| | | | This is progress towards enabling a compute-to-MRF pass.
* i965: Move FS backend structures to a header.Eric Anholt2010-10-115-363/+407
| | | | It's time to start splitting some of this up.
* i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.Eric Anholt2010-10-111-5/+2
| | | | | | While I don't know of any performance changes from this (once extra reg available out of 128), it makes the generated asm a lot cleaner looking.
* i965: Split FS_OPCODE_DISCARD into two steps.Eric Anholt2010-10-111-9/+23
| | | | | | Having the single opcode write then read the reg meant that single instruction opcodes had to consider their source regs to interfere with their dest regs.
* llvmpipe: Use lp_tgsi_info.José Fonseca2010-10-114-30/+31
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* gallivm: More detailed analysis of tgsi shaders.José Fonseca2010-10-114-0/+559
| | | | To allow more optimizations, in particular for direct textures.
* tgsi: Export some names for some tgsi enums.José Fonseca2010-10-112-23/+35
| | | | Useful to give human legible names in other cases.
* gallium: Define C99 restrict keyword where absent.José Fonseca2010-10-111-0/+21
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* gallivm: Eliminate unsigned integer arithmetic from texture coordinates.José Fonseca2010-10-113-42/+32
| | | | | | | | | | | SSE support for 32bit and 16bit unsigned arithmetic is not complete, and can easily result in inefficient code. In most cases signed/unsigned doesn't make a difference, such as for integer texture coordinates. So remove uint_coord_type and uint_coord_bld to avoid inefficient operations to sneak in the future.
* llvmpipe: Remove outdated comment about stencil testing.José Fonseca2010-10-111-9/+2
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* r600g: don't run with scissors.Dave Airlie2010-10-112-0/+92
| | | | | | This could probably be done much nicer, I've spent a day chasing a coherency problem in the kernel, that turned out to be incorrect scissor setup.
* r600g: add TXL opcode support.Dave Airlie2010-10-111-2/+2
| | | | fixes glsl1-2D Texture lookup with explicit lod (Vertex shader)
* r600g: enable vertex samplers.Dave Airlie2010-10-114-9/+21
| | | | | | | | We need to move the texture sampler resources out of the range of the vertex attribs. We could probably improve this using an allocator but this is the simple answer for now. makes mesa-demos/src/glsl/vert-tex work.
* r600g: evergreen has no request size bit in texture word4Dave Airlie2010-10-112-4/+0
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* r600g: fix input/output Z export mixup for evergreen.Dave Airlie2010-10-111-1/+1
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* gallivm: Pass texture coords derivates as scalars.José Fonseca2010-10-104-26/+38
| | | | | We end up treating them as scalars in the end, and it saves some instructions.
* gallivm: Use variables instead of Phis in loops.José Fonseca2010-10-102-42/+23
| | | | With this commit all explicit Phi emission is now gone.
* gallivm: Allow to disable bri-linear filtering with ↵José Fonseca2010-10-103-9/+10
| | | | GALLIVM_DEBUG=no_brilinear runtime option
* gallivm: Fix a long standing bug with nested if-then-else emission.José Fonseca2010-10-101-17/+6
| | | | | | | | | | | | We can't patch true-block at end-if time, as there is no guarantee that the block at the beginning of the true stanza is the same at the end of the true stanza -- other control flow elements may have been emitted half way the true stanza. Although this bug surfaced recently with the commit to skip mip filtering when lod is an integer the bug was always there, although probably it was avoided until now: e.g., cubemap selection nests if-then-else on the else stanza, which does not suffer from the same problem.
* dri/nv10: Fake fast Z clears for pre-nv17 cards.Francisco Jerez2010-10-104-20/+127
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* dri/nouveau: Minor cleanup.Francisco Jerez2010-10-104-23/+22
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