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* gallium: allow setting of the internal stream output offsetZack Rusin2014-03-0729-64/+88
| | | | | | | | | | | | | | | | D3D10 allows setting of the internal offset of a buffer, which is in general only incremented via actual stream output writes. By allowing setting of the internal offset draw_auto is capable of rendering from buffers which have not been actually streamed out to. Our interface didn't allow. This change functionally shouldn't make any difference to OpenGL where instead of an append_bitmask you just get a real array where -1 means append (like in D3D) and 0 means do not append. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meta: use non-ARB shader/program create/delete functionsBrian Paul2014-03-102-30/+30
| | | | | | | The non-ARB versions take GLuint ids, not GLhandleARB. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: s/GLhandleARB/GLuint/ for glGetUniform functionsBrian Paul2014-03-104-29/+29
| | | | | | | The GL specs say the parameter is GLuint, not GLhandleARB. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: rename MESA_FORMAT_X8Z24_UNORM -> MESA_FORMAT_X8_UINT_Z24_UNORMBrian Paul2014-03-1011-24/+24
| | | | | | | To follow the example of MESA_FORMAT_Z24_UNORM_X8_UINT. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: reorder MESA_FORMAT enumsBrian Paul2014-03-104-1530/+1459
| | | | | | | | | The MESA_FORMAT_x enums in formats.h weren't declared in any sort of reasonable order. Now it should be a little more logical. This also required reordering tables in formats.c and s_texfetch.c Reviewed-by: Michel Dänzer <[email protected]> Acked-by: Eric Anholt <[email protected]>
* mesa: trim down format.h commentsBrian Paul2014-03-101-169/+0
| | | | | | | There's no real reason to list all the formats in the comments. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Don't fix-up scalar uniforms for 3 src instructions.Matt Turner2014-03-101-0/+3
| | | | | | | | | | Removes unnecessary MOV instructions in L4D2, TF2, Dota2, and many other Steam games. total instructions in shared programs: 1668126 -> 1657509 (-0.64%) instructions in affected programs: 242235 -> 231618 (-4.38%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disassemble 3 src instructions' rep_ctrl field.Matt Turner2014-03-102-6/+24
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disassemble 3-src operands widths' correctly.Matt Turner2014-03-104-38/+38
| | | | | | | <4,1,1> isn't a real thing. We meant <4,4,1>, i.e., each component of the whole register. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move binding table update packets to binding table setup time.Eric Anholt2014-03-107-39/+17
| | | | | | | | | | | | | | | | | | | This keeps us from needing to reemit all the other stage state just because a surface changed. Improves unoptimized glamor x11perf -f8text by 1.10201% +/- 0.489869% (n=296). [v1] v2: - Drop binding table packets from Gen8 unit state as well. - Pass _3DSTATE_BINDING_TABLE_POINTERS_XS to brw_upload_binding_table, cutting even more code. v3: Don't forget to drop them from 3DSTATE_GS (botched refactor in v2). Signed-off-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Kenneth Graunke <[email protected]> [v1] Signed-off-by: Kenneth Graunke <[email protected]> [v2, v3] Reviewed-by: Eric Anholt <[email protected]> [v3]
* i965: Reorganize the code in brw_upload_binding_tables.Kenneth Graunke2014-03-101-17/+18
| | | | | | | | This makes both the empty and non-empty binding table paths exit through the bottom of the function, which gives us a place to share code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* fix vdpau interop when using -Bsymbolic-functions in ldflagsMaarten Lankhorst2014-03-109-7/+25
| | | | | | | | | | | Explicitly add radeon_drm_winsys_create and nouveau_drm_screen_create to the dynamic list. This will ensure vdpau interop still works even when the user links with -Bsymbolic-functions in hardened builds. Signed-off-by: Maarten Lankhorst <[email protected]> Tested-by: Rachel Greenham <[email protected]> Reported-by: Peter Frühberger <[email protected]> Reviewed-by: Christian König <[email protected]>
* ilo: do not set I915_EXEC_NO_RELOCChia-I Wu2014-03-101-11/+1
| | | | | | | This reverts most of commit d80f0c34b733a874adfdd3a2267e4deec345cc6b. Upon a closer reading, having the presumed offsets written is not enough to set the flag. EXEC_OBJECT_NEEDS_GTT and/or EXEC_OBJECT_WRITE of the reloc entries must also be set appropriately.
* ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu2014-03-104-3/+108
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* ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu2014-03-105-0/+90
| | | | The command writes statistics registers to the specified bo.
* ilo: add some MI commands to GPEChia-I Wu2014-03-104-0/+116
| | | | We will need MI commands that load/store registers.
* ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2014-03-102-2/+16
| | | | | Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for GEN6.
* ilo: print a warning when PPGTT is disabledChia-I Wu2014-03-104-0/+24
| | | | | Despite what the PRMs say, the driver appears to work fine when PPGTT is disabled. But at least print a warning in that case.
* ilo: require hardware logical context supportChia-I Wu2014-03-107-14/+32
| | | | The code paths are not tested for a while, and have some known issues.
* ilo: protect the decode context with a mutexChia-I Wu2014-03-101-7/+20
| | | | The decode context is not thread safe.
* ilo: set I915_EXEC_NO_RELOC when availableChia-I Wu2014-03-102-3/+15
| | | | | The winsys makes it clear that the pipe drivers should write presumed offsets. We can always set I915_EXEC_NO_RELOC when the kernel supports it.
* ilo: move ring types to winsysChia-I Wu2014-03-108-49/+30
| | | | | It results in less code despite that i915_drm.h specifies the ring type as part of the execution flags.
* ilo: winsys may limit the batch buffer sizeChia-I Wu2014-03-107-4/+15
| | | | | | The maximum batch buffer size is determined at the time of drm_intel_bufmgr_gem_init(). Make sure the pipe driver does not exceed the limit.
* ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supportedChia-I Wu2014-03-104-1/+19
| | | | Reading TIMESTAMP register may fail, depending on both kernel and hardware.
* ilo: rework winsys batch buffer functionsChia-I Wu2014-03-105-54/+58
| | | | | | | | | | | Rename intel_winsys_check_aperture_size() to intel_winsys_can_submit_bo(), intel_bo_exec() to intel_winsys_submit_bo(), and intel_winsys_decode_commands() to intel_winsys_decode_bo(). Make a semantic change to ignore intel_context when the ring is not the render ring.
* ilo: replace bo alloc flags by initial domainsChia-I Wu2014-03-108-27/+28
| | | | | | The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed by specifying the initial write domain. The change makes it obvious that we failed to set INTEL_ALLOC_FOR_RENDER in several places.
* ilo: remove intel_bo_get_size()Chia-I Wu2014-03-104-27/+18
| | | | | | Commit bfa8d21759c5f2b5b0885c696842167bd4c64fee uses it to work around a hardware limitation. But there are other ways to do it without the need for intel_bo_get_size().
* ilo: remove intel_bo_get_virtual()Chia-I Wu2014-03-106-114/+141
| | | | Make the map functions return the pointer directly.
* ilo: rework winsys bo reloc functionsChia-I Wu2014-03-106-34/+35
| | | | | | | | | | | | | Rename intel_bo_emit_reloc() to intel_bo_add_reloc(), intel_bo_clear_relocs() to intel_bo_truncate_relocs(), and intel_bo_references() to intel_bo_has_reloc(). Besides, we need intel_bo_get_offset() only to get the presumed offset afer adding a reloc entry. Remove the function and make intel_bo_add_reloc() return the presumed offset. While at it, switch to gem_bo->offset64 from gem_bo->offset.
* ilo: add a wrapper to cast struct intel_boChia-I Wu2014-03-101-23/+28
| | | | It is just drm_intel_bo, but having a wrapper makes the code cleaner.
* ilo: fix DRM_API_HANDLE_TYPE_FD exportChia-I Wu2014-03-101-2/+0
| | | | | It can be exported by drm_intel_bo_gem_export_to_prime(). The code is already in winsys, just not enabled.
* ilo: improve winsys documentation/commentsChia-I Wu2014-03-102-15/+107
| | | | | Document the interface, and add comments as to why some features are enabled and why some checks are made.
* ilo: remove intel_winsys_enable_reuse()Chia-I Wu2014-03-103-13/+3
| | | | It should be an (winsys) implementation detail.
* mesa/glsl: introduce a remap table for uniform locationsTapani Pälli2014-03-106-48/+73
| | | | | | | | | | | | | | | | | Patch adds a remap table for uniforms that is used to provide a mapping from application specified uniform location to actual location in the UniformStorage. Existing UniformLocationBaseScale usage is removed as table can be used to set sequential values for array uniform elements. This mapping helps to implement GL_ARB_explicit_uniform_location so that uniforms locations can be reorganized and handled in a more easy manner. v2: small fixes + rename parameters for merge and split functions (Ian) improve documentation, remove old check for location bounds (Eric) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove _mesa_symbol_table_iterator structureTapani Pälli2014-03-102-99/+0
| | | | | | | | Nothing uses this structure, removal fixes Klocwork error about the possible oom condition in _mesa_symbol_table_iterator_ctor. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: Use proper member name for deleting export shader PM4 stateMichel Dänzer2014-03-101-0/+2
| | | | | | Fixes double-free with some piglit tests using geometry shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: document why texture offset emulation is neededMarek Olšák2014-03-101-1/+2
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* Revert nvc0 part of "nv50: adjust blit_3d handling of ms output textures"Ilia Mirkin2014-03-091-8/+4
| | | | | | | | The nvc0 bits don't appear to work, and I thought I had removed them from the commit. Oops. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nv50: adjust blit_3d handling of ms output texturesIlia Mirkin2014-03-092-8/+16
| | | | | | | | This fixes some unwanted scaling when the output is multisampled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "10.0 10.1" <[email protected]>
* nouveau: fix fence waiting logic in screen destroyIlia Mirkin2014-03-093-7/+27
| | | | | | | | | | | | nouveau_fence_wait has the expectation that an external entity is holding onto the fence being waited on, not that it is merely held onto by the current pointer. Fixes a use-after-free in nouveau_fence_wait when used on the screen's current fence. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75279 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]> Cc: "9.2 10.0 10.1" <[email protected]>
* nouveau: add valid range tracking to nouveau_bufferIlia Mirkin2014-03-096-0/+47
| | | | | | | | | This logic is borrowed from the radeon code. The transfer logic will only get called for PIPE_BUFFER resources, so it shouldn't be necessary to worry about them becoming render targets. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christoph Bumiller <[email protected]>
* gbm: make 'devices' array staticJulien Cristau2014-03-081-1/+1
| | | | | | | It's only used in this one file as far as I can tell, and exporting a symbol named 'devices' from a shared library is a recipe for trouble. Reviewed-by: Emil Velikov <[email protected]>
* automake: make clean the correct git_sha1.h.tmpEmil Velikov2014-03-081-1/+1
| | | | | | | | When building out of tree, the file ends up dangling which may result in a binary with the old git sha. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: fix freeing descriptor buffersChristian König2014-03-081-1/+1
| | | | | | | | That structure member is a pointer, so the loop with the Elements macro only freed up the first entry. Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix leaking the bound state on destruction v2Christian König2014-03-083-0/+10
| | | | | | | v2: rebased on stale pointer fixes Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale state pointersChristian König2014-03-081-9/+3
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid stale pointers in si_delete_shader_selectorChristian König2014-03-081-1/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Revert "winsys/radeon: if there's VRAM-only usage, keep it"Marek Olšák2014-03-081-28/+12
| | | | | | | | This reverts commit 67aef6dafa29fed008ea6065c425a6a92a651be9. It caused GPU hangs. The question is why. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75900
* radeon/vce: fix memory leakChristian König2014-03-081-0/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glcpp: Do not remove spaces to preserve locations.Sir Anthony2014-03-084-5/+5
| | | | | | | | | After preprocessing by glcpp all adjacent spaces were replaced by single one and glsl parser received column-shifted shader source. It negatively affected ast location set up and produced wrong error messages for heavily-spaced shaders. Reviewed-by: Kenneth Graunke <[email protected]>
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