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* intel/fs: Exclude control sources from execution type and region alignment ↵Francisco Jerez2019-02-213-4/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | calculations. Currently the execution type calculation will return a bogus value in cases like: mov_indirect(8) vgrf0:w, vgrf1:w, vgrf2:ud, 32u Which will be considered to have a 32-bit integer execution type even though the actual indirect move operation will be carried out with 16-bit precision. Similarly there's no need to apply the CHV/BXT double-precision region alignment restrictions to such control sources, since they aren't directly involved in the double-precision arithmetic operations emitted by these virtual instructions. Applying the CHV/BXT restrictions to control sources was expected to be harmless if mildly inefficient, but unfortunately it exposed problems at codegen level for virtual instructions (namely the SHUFFLE instruction used for the Vulkan 1.1 subgroup feature) that weren't prepared to accept control sources with an arbitrary strided region. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109328 Reported-by: Mark Janes <[email protected]> Fixes: efa4e4bc5fc "intel/fs: Introduce regioning lowering pass." Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: clone instruction set rather than removing individual entriesTimothy Arceri2019-02-221-3/+3
| | | | | | | | | | | This reduces the time spent in nir_opt_cse() by almost a half. The massif tool from callgrind reported no change in peak memory use with the large doliphin uber shaders I used for testing. Reviewed-by: Thomas Helland<[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Remove extra space in gen4/45/5 field nameJordan Justen2019-02-213-15/+15
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml/gen_bits_header.py: Use regex to strip no alphanum charsJordan Justen2019-02-211-26/+4
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Enable auxiliary buffer supportKenneth Graunke2019-02-211-3/+0
| | | | | | This currently regresses KHR-GL4x.compute_shader.resource-texture, but that's a pre-existing bug (https://bugs.freedesktop.org/109113) which should be fixed up once we have fast clear support.
* iris: Flag ALL_DIRTY_BINDINGS on aux state change.Rafael Antognolli2019-02-213-21/+29
| | | | | | If we change the aux state for a given resource, we need to re-emit the binding table pointers for any stage that has such resource bound. Since we don't track that, flag IRIS_ALL_DIRTY_BINDINGS and emit all of them.
* iris: Skip resolve if there's no context.Rafael Antognolli2019-02-211-1/+9
| | | | | | If iris_resource_get_handle() gets called without a context, we can't resolve the resource. Hopefully it shouldn't be compressed anyway, so let's just add an assert to ensure it's correct.
* iris/clear: Pass on render_condition_enabled.Rafael Antognolli2019-02-211-2/+4
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* iris: Avoid leaking if we fail to allocate the aux buffer.Rafael Antognolli2019-02-211-2/+6
| | | | Otherwise we could leak the aux state map or the aux BO.
* iris: Only resolve compute resources for compute shadersKenneth Graunke2019-02-211-4/+3
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* iris: Fix aux usage in render resolve codeKenneth Graunke2019-02-211-1/+1
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* iris: Pin HiZ buffers when rendering.Rafael Antognolli2019-02-211-0/+8
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* iris: Flush before hiz_exec.Rafael Antognolli2019-02-211-0/+2
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* iris: Allow disabling aux via INTEL_DEBUG optionsKenneth Graunke2019-02-211-2/+4
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* iris: do flush for buffers stillKenneth Graunke2019-02-211-19/+17
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* iris: make surface states for CCS_D tooKenneth Graunke2019-02-211-1/+2
| | | | | | | | CCS_E can fall back to CCS_D with incompatible format views CCS_D is pretty useless without fast clears and we may as well use NONE, but we're surely going to hook those up at some point, so may as well just go ahead and do it now...
* iris: Skip msaa16 on gen < 9.Rafael Antognolli2019-02-211-15/+33
| | | | Also needed to add gen information to KEY_INIT.
* iris: Set program key fields for MCSKenneth Graunke2019-02-211-3/+6
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* iris: don't use hiz for MSAA buffersKenneth Graunke2019-02-211-9/+12
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* iris: some initial HiZ bitsKenneth Graunke2019-02-217-17/+146
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* iris: disable aux for external thingsKenneth Graunke2019-02-211-1/+14
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* iris: Resolves for computeKenneth Graunke2019-02-211-2/+8
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* iris: consider framebuffer parameter for aux usagesKenneth Graunke2019-02-213-9/+13
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* iris: Make blit code use actual aux usagesKenneth Graunke2019-02-211-2/+2
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* iris: store modifier info in resKenneth Graunke2019-02-212-9/+14
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* iris: pin the buffersKenneth Graunke2019-02-211-2/+12
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* iris: resolve before transfer mapsKenneth Graunke2019-02-212-3/+12
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* iris: be sure to skip buffers in resolve codeKenneth Graunke2019-02-211-0/+6
| | | | Buffers don't have ISL surfaces, and this can get us into trouble.
* iris: try to fix copyimage vs copybuffersKenneth Graunke2019-02-211-15/+18
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* iris: actually use the multiple surf states for aux modesKenneth Graunke2019-02-211-10/+30
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* iris: add some draw resolve hooksKenneth Graunke2019-02-216-47/+236
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* iris: blorp using resolve hooksKenneth Graunke2019-02-212-6/+70
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* iris: Initial import of resolve codeKenneth Graunke2019-02-215-8/+1050
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* iris: create aux surface if neededKenneth Graunke2019-02-212-4/+159
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* iris: Fill out SURFACE_STATE entries for each possible aux usageKenneth Graunke2019-02-211-14/+59
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* iris: Fill out res->aux.possible_usagesKenneth Graunke2019-02-211-5/+66
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* iris: Add iris_resource fields for aux surfacesKenneth Graunke2019-02-212-0/+54
| | | | But without fast clears or HiZ per-level tracking just yet.
* iris: Emit default L3 config for the render pipelineJordan Justen2019-02-211-23/+38
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris: Always emit at least one BLEND_STATEKenneth Graunke2019-02-211-1/+8
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* iris: Add missing depth cache flushesKenneth Graunke2019-02-211-0/+5
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* iris: Simplify iris_get_depth_stencil_resourcesKenneth Graunke2019-02-211-5/+1
| | | | | | | | We can safely assume that the given resource is depth, depth/stencil, or stencil already. The stencil-only case is easily detectable with a single format check, and all other cases are handled identically. This saves some CPU overhead.
* iris: Make an IRIS_MAX_MIPLEVELS defineKenneth Graunke2019-02-212-1/+3
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* iris: Store internal_format when getting resource from handle.Rafael Antognolli2019-02-211-0/+1
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* iris: Move create and bind driver hooks to the end of iris_program.cKenneth Graunke2019-02-211-330/+312
| | | | | | | | This just moves the code for dealing with pipe_shader_state / pipe_compute_state / iris_uncompiled_shader to the end of the file. Now that those do precompiles, they want to call the actual compile functions. Putting them at the end eliminates the need for a bunch of prototypes.
* iris: implement clearing render target and depth stencilTimur Kristóf2019-02-211-107/+184
| | | | v2 (Kenneth Graunke): split color/depthstencil cases, fix iris_clear
* iris: Drop XXX about checking for swizzlingKenneth Graunke2019-02-211-2/+1
| | | | | | | | | | | | | Caio noted that this is not necessary on Gen8+: "Before Gen8, there was a historical configuration control field to swizzle address bit[6] for in X/Y tiling modes. This was set in three different places: TILECTL[1:0], ARB_MODE[5:4], and DISP_ARB_CTL[14:13]. For Gen8 and subsequent generations, the swizzle fields are all reserved, and the CPU's memory controller performs all address swizzling modifications." Since we don't support earlier hardware, we can skip it entirely.
* iris: Set HasWriteableRT correctlyKenneth Graunke2019-02-212-1/+45
| | | | A bit of irritating state cross dependency here, but nothing too hard
* iris: Set 3DSTATE_WM::ForceThreadDispatchEnableKenneth Graunke2019-02-211-0/+4
| | | | | | | | The Vulkan driver only sets this if color writes are disabled, which is more conservative - but would require us to inspect blend state. (If color writes are enabled, we don't need to force anything, because the internal signal is already correct. But it shouldn't hurt to do so.)
* iris: Drop XXX about alpha testingKenneth Graunke2019-02-211-3/+1
| | | | | | I was misreading i965 - the 3DSTATE_WM::PixelShaderKillsPixel bit from Gen < 8 needed all of this, but the 3DSTATE_PS_EXTRA bit only needs prog_data->uses_kill.
* iris: improve PIPE_CAP_VIDEO_MEMORY bogus valueAndre Heider2019-02-211-1/+1
| | | | | | -1 is a little too bogus for most games ;) Signed-off-by: Andre Heider <[email protected]>
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